Patents by Inventor Akihiko Ebina

Akihiko Ebina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170038774
    Abstract: An information presenting apparatus includes a system confidence level calculator configured to calculate a system confidence level of autonomous driving control, an information presenter configured to present, to a driver, information on allowableness of an action other than driving, and an information presentation controller configured to control switching of a content of the information presented on the information presenter according to the system confidence level calculated by the system confidence level calculator.
    Type: Application
    Filed: April 25, 2014
    Publication date: February 9, 2017
    Inventor: Akihiko Ebina
  • Publication number: 20170021837
    Abstract: A vehicle information presenting apparatus for use in an autonomous vehicle switches driving control between autonomous driving control, in which the vehicle is driven autonomously, and manual driving control, in which the vehicle is driven manually by a driver. The vehicle information presenting apparatus includes a driving attention level estimator configured to estimate a driving attention level of the driver, and an information presentation controller configured to switch information to present to the driver according to the driving attention level of the driver estimated by the driving attention level estimator.
    Type: Application
    Filed: April 2, 2014
    Publication date: January 26, 2017
    Inventor: Akihiko EBINA
  • Patent number: 9461615
    Abstract: A vibrator element includes a base portion, a vibrating arm extending from the base portion, a first electrode provided on the vibrating arm, a second electrode provided above the first electrode, a piezoelectric body arranged between the first electrode and the second electrode, and an insulating film arranged between the first electrode and the piezoelectric body, in which the material of the first electrode contains TiN, the material of the insulating film contains SiO2, and the material of the piezoelectric body contains AlN.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: October 4, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takashi Yamazaki, Akihiko Ebina, Tsuyoshi Tabata, Hidekazu Yanagisawa
  • Patent number: 9365411
    Abstract: A MEMS device is provided in which, in order to suppress generation of a gas from an inner wall of a space in which a MEMS portion is disposed, the MEMS portion is disposed in a space constituted by at least a silicon nitride film and a silicon film, the silicon film has a first hole, the first hole is filled with a metal film or a metal silicide, and an airtight structure is formed by the metal film or the metal silicide, the silicon nitride film, and the silicon film.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: June 14, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Akihiko Ebina
  • Publication number: 20160159251
    Abstract: A vehicle travel controller carries out automatic travel control of controlling a vehicle to travel automatically based upon travel state information of the vehicle and information on an exterior of the vehicle. An automatic/manual traveling changeover switch is capable of switching between an automatic driving mode in which the automatic travel control is carried out by the vehicle travel controller and a manual driving mode in which the driver drives the vehicle manually. A driving posture controller controls a reclining motor so that the reclining angle of the driver's seat in the automatic driving mode is larger than the reclining angle of the driver's seat in the manual driving mode.
    Type: Application
    Filed: May 27, 2014
    Publication date: June 9, 2016
    Inventors: Akihiko EBINA, Haruhiko SATOU
  • Publication number: 20150340968
    Abstract: A MEMS structure includes: a substrate; a lower electrode disposed on the substrate; an upper electrode including a movable portion disposed facing and spaced from the lower electrode; and a reinforcing portion disposed in the upper electrode so as to extend along an extending direction of the movable portion, the reinforcing portion being composed of a material having a higher Young's modulus than the upper electrode.
    Type: Application
    Filed: April 30, 2015
    Publication date: November 26, 2015
    Inventors: Shogo INABA, Akihiko EBINA
  • Publication number: 20150315011
    Abstract: A MEMS structure includes: a substrate; a lower electrode disposed above the substrate; an upper electrode including a movable portion disposed facing and spaced from the lower electrode; and a projection projecting from a surface of the movable portion on a side facing the lower electrode, the projection being composed of a material different from that of the movable portion.
    Type: Application
    Filed: April 28, 2015
    Publication date: November 5, 2015
    Inventors: Shogo INABA, Akihiko EBINA, Takuya KINUGAWA
  • Publication number: 20150217992
    Abstract: A MEMS device is provided in which, in order to suppress generation of a gas from an inner wall of a space in which a MEMS portion is disposed, the MEMS portion is disposed in a space constituted by at least a silicon nitride film and a silicon film, the silicon film has a first hole, the first hole is filled with a metal film or a metal silicide, and an airtight structure is formed by the metal film or the metal silicide, the silicon nitride film, and the silicon film.
    Type: Application
    Filed: January 22, 2015
    Publication date: August 6, 2015
    Inventor: Akihiko EBINA
  • Publication number: 20150022275
    Abstract: A vibrator element includes a base portion, a vibrating arm extending from the base portion, a first electrode provided on the vibrating arm, a second electrode provided above the first electrode, a piezoelectric body arranged between the first electrode and the second electrode, and an insulating film arranged between the first electrode and the piezoelectric body, in which the material of the first electrode contains TiN, the material of the insulating film contains SiO2, and the material of the piezoelectric body contains AlN.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 22, 2015
    Inventors: Takashi YAMAZAKI, Akihiko EBINA, Tsuyoshi TABATA, Hidekazu YANAGISAWA
  • Patent number: 7592684
    Abstract: A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: September 22, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Takafumi Noda, Masahiro Hayashi, Akihiko Ebina, Masahiko Tsuyuki
  • Publication number: 20070045737
    Abstract: A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.
    Type: Application
    Filed: July 31, 2006
    Publication date: March 1, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takafumi NODA, Masahiro HAYASHI, Akihiko EBINA, Masahiko TSUYUKI
  • Patent number: 7163855
    Abstract: A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: January 16, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Takafumi Noda, Masahiro Hayashi, Akihiko Ebina, Masahiko Tsuyuki
  • Patent number: 7141862
    Abstract: A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: November 28, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Takafumi Noda, Masahiro Hayashi, Akihiko Ebina, Masahiko Tsuyuki
  • Patent number: 7008850
    Abstract: A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: March 7, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Takafumi Noda, Susumu Inoue, Masahiko Tsuyuki, Akihiko Ebina
  • Patent number: 7005328
    Abstract: A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: February 28, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Akihiko Ebina, Susumu Inoue
  • Patent number: 7001812
    Abstract: A fabrication method of a semiconductor device which has on the same semiconductor layer a transistor with a different high voltage gate as well as a high voltage drain and an MNOS memory transistor.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: February 21, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Takafumi Noda, Susumu Inoue, Masahiko Tsuyuki, Akihiko Ebina
  • Patent number: 6995420
    Abstract: A semiconductor device of the present invention has memory cells. Each of the memory cells includes a word gate formed over a semiconductor substrate with a first gate insulating layer interposed therebetween, an impurity layer, and first and second control gates in a shape of sidewalls. Each of the first and second control gates has a rectangular or square cross-sectional shape.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: February 7, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Akihiko Ebina, Susumu Inoue
  • Publication number: 20050148138
    Abstract: A method of manufacturing a semiconductor device that has a high-breakdown-voltage transistor, a low-voltage driving transistor and a MONOS type memory transistor includes a step of forming a stack film that includes at least an oxide silicon layer and a nitride silicon layer over a high-breakdown-voltage transistor forming region where the high-breakdown-voltage transistor is formed, a low-voltage driving transistor forming region where the low-voltage driving transistor is formed and a MONOS type memory transistor forming region where the MONOS type memory transistor is formed in a semiconductor layer, a step of removing the stack film formed in a first gate insulating layer forming region of the high-breakdown-voltage transistor and a step of forming a first gate insulating layer in the high-breakdown-voltage transistor forming region by thermal oxidation.
    Type: Application
    Filed: October 7, 2004
    Publication date: July 7, 2005
    Inventors: Takafumi Noda, Susumu Inoue, Masahiko Tsuyuki, Akihiko Ebina
  • Publication number: 20050130365
    Abstract: A fabrication method of a semiconductor device which has on the same semiconductor layer a transistor with a different high voltage gate as well as a high voltage drain and an MNOS memory transistor.
    Type: Application
    Filed: October 7, 2004
    Publication date: June 16, 2005
    Inventors: Takafumi Noda, Susumu Inoue, Masahiko Tsuyuki, Akihiko Ebina
  • Publication number: 20050118759
    Abstract: A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.
    Type: Application
    Filed: October 7, 2004
    Publication date: June 2, 2005
    Inventors: Takafumi Noda, Susumu Inoue, Masahiko Tsuyuki, Akihiko Ebina