Abstract: A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

Abstract: A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving

Abstract: A semiconductor device is provided that includes a semiconductor layer, first element isolation regions defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating an electric field of the high breakdown voltage transistors, wherein the high breakdown voltage transistors have gate dielectric layers formed by a CVD method.

Abstract: A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.

Abstract: A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

Abstract: A semiconductor device of the present invention includes memory cells. Each of the memory cells includes a word gate formed over a semiconductor substrate with a second gate insulating layer interposed therebetween, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to the impurity layer interposed therebetween is connected with a common contact section. The common contact section includes a contact conductive layer, a stopper insulating layer, and a cap insulating layer. The contact conductive layer is continuous with the first and second control gates. The cap insulating layer is formed at least over the stopper insulating layer.

Abstract: A semiconductor integrated circuit device including a memory cell array in which nonvolatile semiconductor memory devices (memory cells) are arranged in a matrix with a plurality of rows and columns. The nonvolatile semiconductor memory device includes a word gate formed on a semiconductor substrate with a first gate insulating layer interposed, an impurity diffusion layer formed in the semiconductor substrate which forms either a source region or a drain region, and first and second control gates in the shape of sidewalls formed along either side of the word gate. Each of the first and second control gates is disposed on the semiconductor substrate with a second gate insulating layer interposed, and also on the word gate with a side insulating layer interposed. The first and second control gates extend in the column direction. A pair of first and second control gates which are adjacent in the row direction is connected to a common contact section.

Abstract: A semiconductor device 1000 may include first and second switch elements 1000A and 1000B formed in first and second element forming regions 16a and 16b of a SOI layer 10a, respectively. The first and second switch elements 1000A and 1000B form a BiCMOS inverter circuit, and each includes a field effect transistor and a bi-polar transistor. A first p-type body region 50a is electrically connected to an n-type source region 120. The first p-type body region 50a is electrically connected to a first p-type base region 220. A second n-type body region 54a is electrically connected to a second n-type collector region 430. A p-type drain region 330 is electrically connected to a second p-type base region 420.

Abstract: A method for manufacturing a semiconductor device including a non-volatile memory device and a resistance element including a resistance conductive layer is provided. The method comprises the following steps: a step of pattering a stopper layer and a first conductive layer to form a gate layer; a step of patterning the stopper layer, a dielectric layer and the first conductive layer to form a resistance conductive layer; a step of forming sidewall-like control gates on both side surfaces of the gate layer through ONO films at least within a memory region; a step of forming a second conductive layer above the gate layer and the resistance conductive layer; a step of forming a word line by patterning the second conductive layer; and a step of forming a word gate by patterning the gate layer.

Abstract: A semiconductor device 1000 may include an element isolation region 14, an n-type field effect transistor 100 and an npn-type bipolar transistor 200 formed on a SOI substrate 10. A p-type body region 50a may be electrically connected to an n-type source region 120. The p-type body region 50a may be electrically connected to a p-type base region 220. An n-type drain region 130 may be electrically connected to an n-type collector region 230. An n-type source region 120 may be formed structurally isolated from an n-type emitter region 210.

Abstract: Certain embodiments relate to methods for making a semiconductor device that inhibit the formation of a parasitic device. A method for making a semiconductor device includes a delimiting step and a dopant implantation step. The delimiting step partially oxidizes a single-crystal silicon layer provided on a semiconductor substrate 11 with an insulating layer therebetween to form a plurality of isolated single-crystal-silicon-layer segments 13a delimited by the insulating layer 16. In the implantation step, dopant ions 18 are implanted into the single-crystal-silicon-layer segments 13a to activate the single-crystal-silicon-layer segments 13a. In this implantation step, the dopant is implanted into the single-crystal-silicon-layer segments 13a by an implantation energy which is set so that the position of the maximum of the dopant concentration lies at bottom edges Ea and Eb of each single-crystal-silicon-layer segment 13a.

Abstract: A method of manufacturing a semiconductor integrated circuit device including a memory cell array in which non-volatile semiconductor memory devices are arranged in a matrix of a plurality of rows and columns.

Abstract: A semiconductor device may include an element isolation region 14, an npn-type bipolar transistor 200, and a p-type field effect transistor 100, which are formed on a SOI substrate. The bi-polar transistor 200 and the field effect transistor 100 are formed in the same element forming region 16. An n-type body region 52a is electrically connected to an n-type collector region 230. A p-type source region 210 is electrically connected to the n-type collector region 230. A p-type drain region 130 is electrically connected to a p-type base region 220.

Abstract: A method for manufacturing a semiconductor device including a non-volatile memory device and a resistance element including a resistance conductive layer is provided. The method comprises the following steps: a step of pattering a stopper layer and a first conductive layer to form a gate layer; a step of patterning the stopper layer, a dielectric layer and the first conductive layer to form a resistance conductive layer; a step of forming sidewall-like control gates on both side surfaces of the gate layer through ONO films at least within a memory region; a step of forming a second conductive layer above the gate layer and the resistance conductive layer; a step of forming a word line by patterning the second conductive layer; and a step of forming a word gate by patterning the gate layer.

Abstract: A method of manufacturing a semiconductor device having the memory region which has a MONOS type memory cell and a logic circuit region which has a peripheral circuit, including the following steps. A stopper layer and a predetermined region of a first conductive layer within the memory region are patterned, but a stopper layer and a first conductive layer within the logic circuit region are not pattered. Side-wall shaped control gates are formed at least on both sides of the first conductive layer within the memory region with an ONO film interposed. The first conductive layer within the logic circuit region is patterned to form a gate electrode of a MOS transistor. Surfaces of gate electrodes and source or drain regions of the non-volatile memory device and the MOS transistor are silicided. After a second insulating layer is formed, the second insulating layer is polished so that the stopper layer within the memory region is exposed and the gate electrode within the logic circuit region is not exposed.

Abstract: A semiconductor integrated circuit comprising: a first power line which supplies a first voltage potential; a second power line which supplies a second voltage potential that is lower than the first voltage potential; a voltage regulator circuit connected electrically to the first and second power lines; a third power line which supplies a constant voltage generated by a voltage regulator circuit, with reference to the first voltage potential; and an operating circuit connected electrically to the first and third power lines. At least one transistor configuring the voltage regulator circuit is a partially-depleted SOI field-effect transistor in which a body region and a source region are connected electrically. At least one transistor configuring the operating circuit is a partially-depleted SOI field-effect transistor in which a body region is in an electrically floating state.

Abstract: A semiconductor device of the present invention includes memory cells. Each of the memory cells includes a word gate formed over a semiconductor substrate with a second gate insulating layer interposed therebetween, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to the impurity layer interposed therebetween is connected with a common contact section. The common contact section includes a contact conductive layer, a stopper insulating layer, and a cap insulating layer. The contact conductive layer is continuous with the first and second control gates. The cap insulating layer is formed at least over the stopper insulating layer.

Abstract: A semiconductor device of the present invention has memory cells. Each of the memory cells includes a word gate formed over a semiconductor substrate with a first gate insulating layer interposed therebetween, an impurity layer, and first and second control gates in a shape of sidewalls. Each of the first and second control gates has a rectangular or square cross-sectional shape.

Abstract: A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

Abstract: A method of manufacturing a semiconductor device having the memory region which has a MONOS type memory cell and a logic circuit region which has a peripheral circuit, including the following steps. A stopper layer and a predetermined region of a first conductive layer within the memory region are patterned, but a stopper layer and a first conductive layer within the logic circuit region are not pattered. Side-wall shaped control gates are formed at least on both sides of the first conductive layer within the memory region with an ONO film interposed. The first conductive layer within the logic circuit region is patterned to form a gate electrode of a MOS transistor. Surfaces of gate electrodes and source or drain regions of the non-volatile memory device and the MOS transistor are silicided. After a second insulating layer is formed, the second insulating layer is polished so that the stopper layer within the memory region is exposed and the gate electrode within the logic circuit region is not exposed.