Abstract: A SOI-structure MOS field-effect transistor. In this transistor, a gate electrode and a p− region that is a body region are placed into electrical contact by a PN junction portion. An n+-type portion of the PN junction portion is in electrical contact with the gate electrode and a p+-type portion of the PN junction portion is in electrical contact with a p− region. When a positive voltage is applied to the gate electrode, the above configuration ensures that a reverse voltage is applied to the PN junction portion, so that only a small current on the order of the reverse leakage current of the PN junction flows along the path from the gate electrode, to the PN junction portion and the body region, and into the source region.

Abstract: A method of fabricating a semiconductor device including the following steps of: forming a first insulating layer, a first conductive layer and a stopper layer over a semiconductor layer; forming a mask insulating layer on the first conductive layer in a logic circuit region; forming a conductive layer in a formation region of word gate layers and common contact sections and forming gate electrodes; anisotropically etching the second conductive layer to form control gates in the shape of sidewalls and a conductive layer of the common contact sections, in a memory region; and patterning the third conductive layer and the first conductive layer to form word gates and word lines.

Abstract: A dynamic threshold-voltage MOSFET (DTMOS) enables a low power consumption, even during use under conditions of a comparatively high gate voltage. A first contact portion and a gate electrode are placed in electrical contact by a resistance portion. A part of an interconnecting portion is utilized as the resistance portion, by making the width of the part of the interconnecting portion smaller than the width of a remaining part of the interconnecting portion. The forward-direction current flowing through a PN junction formed by a body region and a source region is limited by the resistance portion, even when a comparatively high voltage is applied to the gate electrode. Thus the current between the body region and the source region can be held low. As a result, the power consumption can be reduced, even when the MOS field-effect transistor is used under conditions of a comparatively high gate voltage.

Abstract: A semiconductor device may include an element isolation region 14, an npn-type bipolar transistor 200, and a p-type field effect transistor 100, which are formed on a SOI substrate. The bi-polar transistor 200 and the field effect transistor 100 are formed in the same element forming region 16. An n-type body region 52a is electrically connected to an n-type collector region 230. A p-type source region 210 is electrically connected to the n-type collector region 230. A p-type drain region 130 is electrically connected to a p-type base region 220.

Abstract: A method of manufacturing a semiconductor integrated circuit device having nonvolatile semiconductor memory devices includes the following steps (a) to (k): (a) A step of forming an element isolation region, (b) a step of forming a first gate insulating layer and a laminate including a first conductive layer for a word gate and having a plurality of openings extending in a first direction, (c) a step of forming second gate insulating layers, (d) a step of forming side insulating layers on both sides of the first conductive layer, (e) a step of forming a second conductive layer over the entire surface, (f) a step of forming a first mask layer at least in a region in which a common contact section is formed, (g) a step of anisotropically etching the second conductive layer, thereby forming first and second control gates in the shape of sidewalls and forming a contact conductive layer at least in a region in which the common contact section is formed, (h) a step of forming an impurity diffusion layer which forms

Abstract: A semiconductor device 1000 may include an element isolation region 14, an n-type field effect transistor 100 and an npn-type bipolar transistor 200 formed on a SOI substrate 10. A p-type body region 50a may be electrically connected to an n-type source region 120. The p-type body region 50a may be electrically connected to a p-type base region 220. An n-type drain region 130 may be electrically connected to an n-type collector region 230. An n-type source region 120 may be formed structurally isolated from an n-type emitter region 210.

Abstract: A semiconductor device 1000 may include first and second switch elements 1000A and 1000B formed in first and second element forming regions 16a and 16b of a SOI layer 10a, respectively. The first and second switch elements 1000A and 1000B form a BiCMOS inverter circuit, and each includes a field effect transistor and a bi-polar transistor. A first p-type body region 50a is electrically connected to an n-type source region 120. The first p-type body region 50a is electrically connected to a first p-type base region 220. A second n-type body region 54a is electrically connected to a second n-type collector region 430. A p-type drain region 330 is electrically connected to a second p-type base region 420.

Abstract: A semiconductor integrated circuit device including a memory cell array in which nonvolatile semiconductor memory devices (memory cells) are arranged in a matrix with a plurality of rows and columns. The nonvolatile semiconductor memory device includes a word gate formed on a semiconductor substrate with a first gate insulating layer interposed, an impurity diffusion layer formed in the semiconductor substrate which forms either a source region or a drain region, and first and second control gates in the shape of sidewalls formed along either side of the word gate. Each of the first and second control gates is disposed on the semiconductor substrate with a second gate insulating layer interposed, and also on the word gate with a side insulating layer interposed. The first and second control gates extend in the column direction. A pair of first and second control gates which are adjacent in the row direction is connected to a common contact section.

Abstract: A fabrication method of the present invention includes the following steps: A step of forming gate electrodes in a logic circuit region; a step of forming first and second protective insulating layers in the logic circuit region; a step of forming a first gate insulating layer and a word gate layer in a memory region; a step of forming a second gate insulating layer on a semiconductor substrate and forming side insulating layers on both sides of the word gate layer in the memory region; a step of anisotropically etching the second conductive layer, thereby forming control gates in the shape of sidewalls and a conductive layer continuous with the control gates in regions in which common contact sections are formed; a step of removing the first and second protective insulating layers; and a step of forming impurity layers which form either a source or drain.

Abstract: Certain embodiments relate to methods for making a semiconductor device that inhibit the formation of a parasitic device. A method for making a semiconductor device includes a delimiting step and a dopant implantation step. The delimiting step partially oxidizes a single-crystal silicon layer provided on a semiconductor substrate 11 with an insulating layer therebetween to form a plurality of isolated single-crystal-silicon-layer segments 13a delimited by the insulating layer 16. In the implantation step, dopant ions 18 are implanted into the single-crystal-silicon-layer segments 13a to activate the single-crystal-silicon-layer segments 13a. In this implantation step, the dopant is implanted into the single-crystal-silicon-layer segments 13a by an implantation energy which is set so that the position of the maximum of the dopant concentration lies at bottom edges Ea and Eb of each single-crystal-silicon-layer segment 13a.

Abstract: A semiconductor integrated circuit comprising: a first power line which supplies a first voltage potential; a second power line which supplies a second voltage potential that is lower than the first voltage potential; a voltage regulator circuit connected electrically to the first and second power lines; a third power line which supplies a constant voltage generated by a voltage regulator circuit, with reference to the first voltage potential; and an operating circuit connected electrically to the first and third power lines. At least one transistor configuring the voltage regulator circuit is a partially-depleted SOI field-effect transistor in which a body region and a source region are connected electrically. At least one transistor configuring the operating circuit is a partially-depleted SOI field-effect transistor in which a body region is in an electrically floating state.

Abstract: A SOI-structure MOS field-effect transistor. In this transistor, agate electrode and a p− region that is a body region are placed into electrical contact by a PN junction portion. An n+-type portion of the PN junction portion is in electrical contact with the gate electrode and a p+-type portion of the PN junction portion is in electrical contact with a p− region. When a positive voltage is applied to the gate electrode, the above configuration ensures that a reverse voltage is applied to the PN junction portion, so that only a small current on the order of the reverse leakage current of the PN junction flows along the path from the gate electrode, to the PN junction portion and the body region, and into the source region.

Abstract: A test circuit for evaluating the characteristics of an component formed on the surface of a semi-conductor substrate. The test circuit comprises at least two MOS field effect transistors having the same gate width and different gate lengths, and measuring electrodes mounted on opposite ends of each gate and enageable with probes when measuring the test circuit. The test circuit measures typical characteristic data of MOSFETs to be used in a semiconductor device with good match by an electrical means.