Patents by Inventor Akihiko Furukawa

Akihiko Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200135908
    Abstract: Provided is a technology for obtaining a drain current of a sufficient magnitude in a field effect transistor using a nitride semiconductor. A channel layer that is Alx1Iny1Ga1-x1-y1N is formed on an upper surface of a semiconductor substrate, and on an upper surface of the channel layer, a barrier layer that is Alx2Iny2Ga1-x2-y2N having a band gap larger than that of the channel layer is formed. Then, on an upper surface of the barrier layer, a gate insulating film that is an insulator or a semiconductor and has a band gap larger than that of the barrier layer is at least partially formed, and a gate electrode is formed on an upper surface of the gate insulating film. Then, heat treatment is performed while a positive voltage is applied to the gate electrode.
    Type: Application
    Filed: May 31, 2017
    Publication date: April 30, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takuma NANJO, Tetsuro HAYASHIDA, Koji YOSHITSUGU, Akihiko FURUKAWA
  • Publication number: 20200127099
    Abstract: A substrate is made of gallium-nitride-based material. The n-type layer is disposed on a first surface of the substrate. A p-type layer is disposed on the n-type layer, and constitutes, along with the n-type layer, a semiconductor layer on the first surface of the substrate, the semiconductor layer being provided with a mesa shape having a bottom surface, a side surface, and a top surface. An anode electrode is disposed on the p-type layer. A cathode electrode is disposed on a second surface of the substrate. An insulating film continuously extends over the bottom surface and the top surface to cover the side surface. The top surface is provided with at least one trench. The at least one trench includes a trench filled with the insulating film.
    Type: Application
    Filed: February 10, 2017
    Publication date: April 23, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuro HAYASHIDA, Takuma NANJO, Tatsuro WATAHIKI, Akihiko FURUKAWA
  • Patent number: 10559659
    Abstract: A power semiconductor device includes an emitter electrode disposed on a semiconductor substrate and through which a main current flows, a conductive layer that is disposed on the emitter electrode and is not a sintered compact, and a sintered metal layer that is disposed on the conductive layer and is a sintered compact. The sintered metal layer has a size to cover all the emitter electrode in plan view, and has higher heat conductivity than the conductive layer. The power semiconductor device can improve heat dissipation performance and adhesion.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: February 11, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Atsufumi Inoue, Seiji Oka, Tsuyoshi Kawakami, Akihiko Furukawa, Hidetada Tokioka, Mutsumi Tsuda, Yasushi Fujioka
  • Publication number: 20200006538
    Abstract: Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.
    Type: Application
    Filed: December 19, 2018
    Publication date: January 2, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryu KAMIBABA, Tetsuo TAKAHASHI, Akihiko FURUKAWA
  • Patent number: 10486375
    Abstract: A production method for a fiber-reinforced plastic, in which a preform made of a reinforcing fiber substrate and having a three-dimensional shape and an inner mold operatable in a lateral direction different from an up-down direction are disposed in a mold cavity formed by an upper mold and a lower mold, and a state in which a plate thickness of the preform has been made greater than the thickness of a molded article to be obtained is brought about, and a matrix resin is injected and impregnated into the preform, and, after that, at least one of the upper mold and the lower mold is operated toward the other and the inner mold is operated in the lateral direction to pressurize the preform, whereby the thickness of the preform is controlled so as to be equal to a predetermined product's thickness, and subsequently the matrix resin is hardened by heating to obtain the molded article, and a production apparatus for a fiber-reinforced plastic for use in the production method.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: November 26, 2019
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Naofumi Hosokawa, Hiroshi Odani, Masato Furukawa, Masaaki Yamasaki, Akihiko Shirahase
  • Publication number: 20190326424
    Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.
    Type: Application
    Filed: January 23, 2019
    Publication date: October 24, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryu KAMIBABA, Tetsuo TAKAHASHI, Akihiko FURUKAWA
  • Publication number: 20190109220
    Abstract: In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihiko FURUKAWA, Shoichi Orita, Hiroki Muraoka, Atsushi Narazaki, Tsuyoshi Kawakami, Yuji Murakami
  • Publication number: 20190058037
    Abstract: A power semiconductor device includes an emitter electrode disposed on a semiconductor substrate and through which a main current flows, a conductive layer that is disposed on the emitter electrode and is not a sintered compact, and a sintered metal layer that is disposed on the conductive layer and is a sintered compact. The sintered metal layer has a size to cover all the emitter electrode in plan view, and has higher heat conductivity than the conductive layer. The power semiconductor device can improve heat dissipation performance and adhesion.
    Type: Application
    Filed: December 21, 2016
    Publication date: February 21, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Atsufumi INOUE, Seiji OKA, Tsuyoshi KAWAKAMI, Akihiko FURUKAWA, Hidetada TOKIOKA, Mutsumi TSUDA, Yasushi FUJIOKA
  • Patent number: 10192977
    Abstract: In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 29, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihiko Furukawa, Shoichi Orita, Hiroki Muraoka, Atsushi Narazaki, Tsuyoshi Kawakami, Yuji Murakami
  • Patent number: 10192978
    Abstract: A semiconductor apparatus includes: a p-type base layer provided on a top surface side of an n-type drift layer; an n-type emitter layer provided on a top surface side of the p-type base layer; a first control electrode having a trench gate electrode embedded so as to reach from a surface layer of the n-type emitter layer to the n-type drift layer; a second control electrode having a trench gate electrode embedded so as to reach from the p-type base layer to the n-type drift layer; a p-type collector layer provided on a bottom surface side of the n-type drift layer; and a diode whose anode side and cathode side are connected to the first control electrode and the second control electrodes, respectively. It is possible to improve the controllability of dV/dt by a gate resistor.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: January 29, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Satoshi Okuda, Akihiko Furukawa, Tsuyoshi Kawakami
  • Patent number: 10147699
    Abstract: In a pressure contact type semiconductor apparatus, a second intermediate electrode on a second semiconductor chip has one or more second through holes. The one or more second through holes are fluidly separated from a space hermetically sealed by a cylindrical body, a first common electrode plate and a second common electrode plate. The pressure contact type semiconductor apparatus thereby has high reliability.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: December 4, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Satoshi Okuda, Akihiko Furukawa, Tomohiro Ikeda
  • Publication number: 20180277508
    Abstract: In a pressure contact type semiconductor apparatus, a second intermediate electrode on a second semiconductor chip has one or more second through holes. The one or more second through holes are fluidly separated from a space hermetically sealed by a cylindrical body, a first common electrode plate and a second common electrode plate. The pressure contact type semiconductor apparatus thereby has high reliability.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 27, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Satoshi OKUDA, Akihiko FURUKAWA, Tomohiro IKEDA
  • Patent number: 9985093
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 29, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro Kagawa, Akihiko Furukawa, Shiro Hino, Hiroshi Watanabe, Masayuki Imaizumi
  • Publication number: 20170162649
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro KAGAWA, Akihiko FURUKAWA, Shiro HINO, Hiroshi WATANABE, Masayuki IMAIZUMI
  • Patent number: 9614029
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: April 4, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuhiro Kagawa, Akihiko Furukawa, Shiro Hino, Hiroshi Watanabe, Masayuki Imaizumi
  • Patent number: 9536942
    Abstract: A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: January 3, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Kenji Hamada, Kohei Ebihara, Akihiko Furukawa, Yuji Murakami
  • Publication number: 20160372585
    Abstract: In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.
    Type: Application
    Filed: October 29, 2014
    Publication date: December 22, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihiko FURUKAWA, Shoichi ORITA, Hiroki MURAOKA, Atsushi NARAZAKI, Tsuyoshi KAWAKAMI, Yuji MURAKAMI
  • Patent number: 9525057
    Abstract: A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 20, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naruhisa Miura, Shiro Hino, Akihiko Furukawa, Yuji Abe, Shuhei Nakata, Masayuki Imaizumi, Yasuhiro Kagawa
  • Patent number: 9508792
    Abstract: An electric field buffer layer is formed so as to surround an active region. The electric field buffer layer includes a plurality of P-type impurity layers. Each of the P-type impurity layers includes P-type implantation layers and P-type diffusion layers that are formed so as to respectively surround the P-type implantation layers and contain P-type impurities at a concentration lower than that of the P-type implantation layers. A first P-type implantation layer is formed to be in contact with or to partially overlap the active region. Each of the P-type diffusion layers is formed to have an expansion to a degree to which the first P-type diffusion layer is in contact with or overlaps a second P-type diffusion layer. Intervals between the P-type implantation layers increase from the active region toward the outer peripheral portion of the semiconductor substrate.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: November 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Ze Chen, Akito Nishii, Fumihito Masuoka, Katsumi Nakamura, Akihiko Furukawa, Yuji Murakami
  • Patent number: 9496344
    Abstract: In a JBS diode using a wide band gap semiconductor, the wide band gap semiconductor has a large built-in voltage, which sometimes causes difficulties for the pn diode portion to turn on, resulting in a problem that resistance to surge currents is not sufficiently ensured. In order to solve this problem, in the wide-band-gap JBS diode, a pn junction of the pn diode is formed away from the Schottky electrode, and well regions are formed so as to have a width narrowed at a portion away from the Schottky electrode.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 15, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Akihiko Furukawa, Masayuki Imaizumi, Yuji Abe