Patents by Inventor Akihiko Furukawa

Akihiko Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140203393
    Abstract: A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.
    Type: Application
    Filed: July 31, 2012
    Publication date: July 24, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Yoshiyuki Nakaki, Yoshio Fujii, Hiroshi Watanabe, Shuhei Nakata, Kohei Ebihara, Akihiko Furukawa
  • Patent number: 8785931
    Abstract: A semiconductor device capable of rapidly and accurately sensing the information regarding the temperature of a semiconductor transistor contained therein. A MOSFET includes a plurality of cells, and includes a main cell group including a cell for supplying a current to a load among the plurality of cells, and a sense cell group including a cell for sensing temperature information regarding the temperature of the MOSFET thereamong. The main cell group and the sense cell group have different temperature characteristics showing changes in electrical characteristics to changes in temperature. A temperature sensing circuit senses the temperature of the MOSFET based on, for example, a value of a main current flowing through the main cell group and a value of a sense current flowing through the sense cell group.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: July 22, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinichi Kinouchi, Hiroshi Nakatake, Yuji Ebiike, Akihiko Furukawa, Masayuki Imaizumi
  • Patent number: 8779855
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Iida, Akihiko Furukawa, Satoshi Yamakawa, Tsuyoshi Kawakami, Masao Kondo, Yutaka Hoshino
  • Patent number: 8716717
    Abstract: A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: May 6, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Naruhisa Miura, Yasuhiro Kagawa, Kenji Hamada, Yoshiyuki Nakaki
  • Publication number: 20140077232
    Abstract: A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.
    Type: Application
    Filed: March 7, 2012
    Publication date: March 20, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Akihiko Furukawa, Yukiyasu Nakao, Tomokatsu Watanabe, Masayoshi Tarutani, Yuji Ebiike, Masayuki Imaizumi, Sunao Aya
  • Publication number: 20140001472
    Abstract: A silicon carbide semiconductor device including an SBD measuring a temperature of a silicon carbide semiconductor element. The silicon carbide semiconductor device includes a MOSFET formed on a silicon carbide epitaxial substrate, and an SBD section measuring a temperature of the MOSFET. The SBD section includes an n-type cathode region in a surface portion of a silicon carbide drift layer; an anode titanium electrode formed on the cathode region, the electrode serving as a Schottky electrode; an n-type cathode contact region of a higher concentration than that of the cathode region, formed in the surface portion of the silicon carbide drift layer to make contact with the cathode region; a cathode ohmic electrode formed on the cathode contact region; and a first p-type well region formed within the silicon carbide drift layer to surround peripheries of the cathode region and the cathode contact region.
    Type: Application
    Filed: May 18, 2011
    Publication date: January 2, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Akihiko Furukawa, Yasuhiro Kagawa, Naruhisa Miura, Masayuki Imaizumi
  • Publication number: 20130285140
    Abstract: A trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device includes a gate electrode embedded into a trench penetrating a base region. The gate electrode is disposed into a lattice shape in a planar view, and a protective diffusion layer is formed in a drift layer at the portion underlying thereof. At least one of blocks divided by the gate electrode is a protective contact region on which the trench is entirely formed. A protective contact for connecting the protective diffusion layer at a bottom portion of the trench and a source electrode is disposed on the protective contact region.
    Type: Application
    Filed: December 5, 2011
    Publication date: October 31, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yasuhiro Kagawa, Akihiko Furukawa, Shiro Hino, Hiroshi Watanabe, Masayuki Imaizumi
  • Publication number: 20130265109
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Application
    Filed: May 29, 2013
    Publication date: October 10, 2013
    Inventors: Tetsuya IIDA, Akihiko FURUKAWA, Satoshi YAMAKAWA, Tsuyoshi KAWAKAMI, Masao KONDO, Yutaka HOSHINO
  • Patent number: 8492836
    Abstract: In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: July 23, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Shiro Hino, Akihiko Furukawa
  • Patent number: 8493152
    Abstract: A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Satoshi Yamakawa
  • Publication number: 20130168700
    Abstract: In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.
    Type: Application
    Filed: June 24, 2010
    Publication date: July 4, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventors: Akihiko Furukawa, Yasuhiro Kagawa, Naruhisa Miura, Shiro Hino, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Masayuki Imaizumi
  • Publication number: 20130153900
    Abstract: A semiconductor device capable of rapidly and accurately sensing the information regarding the temperature of a semiconductor transistor contained therein. A MOSFET includes a plurality of cells, and includes a main cell group including a cell for supplying a current to a load among the plurality of cells, and a sense cell group including a cell for sensing temperature information regarding the temperature of the MOSFET thereamong. The main cell group and the sense cell group have different temperature characteristics showing changes in electrical characteristics to changes in temperature. A temperature sensing circuit senses the temperature of the MOSFET based on, for example, a value of a main current flowing through the main cell group and a value of a sense current flowing through the sense cell group.
    Type: Application
    Filed: August 26, 2011
    Publication date: June 20, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shinichi Kinouchi, Hiroshi Nakatake, Yuji Ebiike, Akihiko Furukawa, Masayuki Imaizumi
  • Patent number: 8461927
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: June 11, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Satoshi Yamakawa, Tetsuya Iida, Masao Kondo, Yutaka Hoshino
  • Publication number: 20130140582
    Abstract: The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer (101) including a plurality of P-type implantation layers having a relatively low concentration of P-type impurity is formed adjacent to an active region (2). The RESURF layer (101) includes a first RESURF layer (11), a second RESURF layer (12), a third RESURF layer (13), a fourth RESURF layer (14), and a fifth RESURF layer (15) that are arranged sequentially from the P-type base (2) side so as to surround the P-type base (2). The second RESURF layer (12) is configured with small regions (11?) having an implantation amount equal to that of the first RESURF layer (11) and small regions (13?) having an implantation amount equal to that of the third RESURF layer (13) being alternately arranged in multiple.
    Type: Application
    Filed: April 15, 2011
    Publication date: June 6, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Naruhisa Miura, Yasuhiro Kagawa, Kenji Hamada, Yoshiyuki Nakaki
  • Publication number: 20130020587
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.
    Type: Application
    Filed: February 8, 2011
    Publication date: January 24, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Akihiko Furukawa, Yukiyasu Nakao, Masayuki Imaizumi
  • Publication number: 20130009709
    Abstract: A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.
    Type: Application
    Filed: September 15, 2012
    Publication date: January 10, 2013
    Inventors: Tsuyoshi KAWAKAMI, Akihiko FURUKAWA, Satoshi YAMAKAWA
  • Patent number: 8330544
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Satoshi Yamakawa, Tetsuya Iida, Masao Kondo, Yutaka Hoshino
  • Patent number: 8314658
    Abstract: A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Satoshi Yamakawa
  • Publication number: 20120205669
    Abstract: In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.
    Type: Application
    Filed: October 14, 2009
    Publication date: August 16, 2012
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Shiro Hino, Akihiko Furukawa
  • Publication number: 20120133431
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 31, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Tsuyoshi KAWAKAMI, Akihiko FURUKAWA, Satoshi YAMAKAWA, Tetsuya IIDA, Masao KONDO, Yutaka HOSHINO