Patents by Inventor Akihiko Ishibashi

Akihiko Ishibashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070290230
    Abstract: A nitride semiconductor device according to the present invention includes a p-type nitride semiconductor layer, an n-type nitride semiconductor layer, and an active layer interposed between the p-type nitride semiconductor layer and the n-type nitride semiconductor layer. The p-type nitride semiconductor layer includes: a first p-type nitride semiconductor layer containing Al and Mg; and a second p-type nitride semiconductor layer containing Mg. The first p-type nitride semiconductor layer is located between the active layer and the second p-type nitride semiconductor layer, and the second p-type nitride semiconductor layer has a greater band gap than a band gap of the first p-type nitride semiconductor layer.
    Type: Application
    Filed: September 24, 2004
    Publication date: December 20, 2007
    Inventors: Yasutoshi Kawaguchi, Toshitaka Shimamoto, Akihiko Ishibashi, Isao Kidoguchi, Toshiya Yokogawa
  • Publication number: 20070228395
    Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.
    Type: Application
    Filed: June 7, 2007
    Publication date: October 4, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
  • Publication number: 20070217460
    Abstract: A process for producing a nitride semiconductor according to the present invention includes: step (A) of provided an n-GaN substrate 101; step (B) of forming on the substrate 101 a plurality of stripe ridges having upper faces which are parallel to a principal face of the substrate 101; step (C) of selectively growing AlxGayInzN crystals (0?x, y, z?1: x+y+z=1) 104 on the upper faces of the plurality of stripe ridges, the AlxGayInzN crystals containing an n-type impurity at a first concentration; and step (D) of growing an Alx?Gay?Inz?N crystal (0?x?, y?, z??1: x?+y?+z?=1) 106 on the AlxGayInzN crystals 104, the Alx?Gay?Inz?N crystal 106 containing an n-type impurity at a second concentration which is lower than the first concentration, and linking every two adjoining AlxGayInzN crystals 104 with the Alx?Gay?Inz?N crystal 106 to form one nitride semiconductor layer 120.
    Type: Application
    Filed: April 20, 2005
    Publication date: September 20, 2007
    Inventors: Akihiko Ishibashi, Toshiya Yokogawa, Toshitaka Shimamoto, Yoshiaki Hasegawa, Yasutoshi Kawaguchi, Isao Kidoguchi
  • Publication number: 20070187700
    Abstract: The present invention provides a method of manufacturing a Group III nitride substrate that has less variations in in-plane carrier concentration and includes crystals grown at a high growth rate.
    Type: Application
    Filed: March 30, 2007
    Publication date: August 16, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi, Akihiko Ishibashi
  • Patent number: 7221037
    Abstract: The present invention provides a method of manufacturing a Group III nitride substrate that has less variations in in-plane carrier concentration and includes crystals grown at a high growth rate.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: May 22, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi, Akihiko Ishibashi
  • Patent number: 7176115
    Abstract: The present invention provides a manufacturing method that allows a Group III nitride substrate with a low dislocation density to be manufactured, and a semiconductor device that is manufactured using the manufacturing method. The manufacturing method includes, in an atmosphere including nitrogen, allowing a Group III element and the nitrogen to react with each other in an alkali metal melt to cause generation and growth of Group III nitride crystals. In the manufacturing method, a plurality of portions of a Group III nitride semiconductor layer are prepared, selected as seed crystals, and used for at least one of the generation and the growth of the Group III nitride crystals, and then surfaces of the seed crystals are brought into contact with the alkali metal melt.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: February 13, 2007
    Assignees: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi, Akihiko Ishibashi, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
  • Patent number: 7160748
    Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: January 9, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
  • Publication number: 20060166478
    Abstract: A method for fabricating nitride semiconductor devices according to the present invention includes the steps of: (A) providing a nitride semiconductor substrate, which will be split into chip substrates, which includes device portions that will function as the respective chip substrates when the substrate is split and interdevice portions that connect the device portions together, and in which the average thickness of the interdevice portions is smaller than the thickness of the device portions; (B) defining a masking layer, which has striped openings over the device portions, on the upper surface of the nitride semiconductor substrate; (C) selectively growing nitride semiconductor layers on portions of the upper surface of the nitride semiconductor substrate, which are exposed through the openings of the masking layer; and (D) cleaving the nitride semiconductor substrate along the interdevice portions of the nitride semiconductor substrate, thereby forming nitride semiconductor devices on the respectively sp
    Type: Application
    Filed: March 9, 2004
    Publication date: July 27, 2006
    Inventors: Gaku Sugahara, Yasutoshi Kawaguchi, Akihiko Ishibashi, Isao Kidoguchi, Toshiya Yokogawa
  • Publication number: 20060145165
    Abstract: The present invention relates to a semiconductor light emitting device comprising a sapphire substrate 11; a u-GaN layer 12 that is formed on top of the substrate 11 and that comprises a plurality of concave portions 121 formed into band-like shapes with predetermined intervals therebetween; a regrown u-GaN layer 13 formed on the u-Ga layer 12; a layered structure that is formed on the u-GaN layer 13 comprises an n-GaN layer 15, an active layer 16, and a p-GaN layer 19; an n-type electrode 24 formed on the n-GaN layer 15 exposed by removing a potion of the layered structure; and a transparent p-type electrode 20 formed on the p-GaN layer 19, wherein the p-type electrode 20 is an emission detection surface, and an air layer S is formed between the bottom surface of the u-GaN layer 13 and the concave portions 121.
    Type: Application
    Filed: February 23, 2006
    Publication date: July 6, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Akihiko Ishibashi, Toshiya Yokogawa, Kiyoshi Ohnaka, Susumu Koike
  • Patent number: 7056756
    Abstract: A method for fabricating a nitride semiconductor laser device including a step to expose surfaces of an n-type nitride semiconductor layer (102) and a p-type nitride semiconductor layer (108); a step to cover the surface of the multi-layered semiconductor; with an insulating film (109) that has a thickness greater than the difference in levels between the exposed surface of the n-type nitride semiconductor layer (102) and the outermost surface of the p-type nitride semiconductor layer (108); a step to flatten the surface of the insulating film (109); and a step to form an n-type electrode (111) and a p-type electrode (110) electrically connected to the n-type nitride semiconductor layer (102) and the p-type nitride semiconductor layer (108), respectively. This method makes it possible to obtain a nitride semiconductor laser device that is highly reliable and exhibits an excellent heat diffusing property.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: June 6, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Gaku Sugahara, Yoshiaki Hasegawa, Akihiko Ishibashi, Toshiya Yokogawa
  • Patent number: 7030417
    Abstract: The present invention relates to a semiconductor light emitting device comprising a sapphire substrate 11; a u-GaN layer 12 that is formed on top of the substrate 11 and that comprises a plurality of concave portions 121 formed into band-like shapes with predetermined intervals therebetween; a regrown u-GaN layer 13 formed on the u-Ga layer 12; a layered structure that is formed on the u-GaN layer 13 comprises an n-GaN layer 15, an active layer 16, and a p-GaN layer 19; an n-type electrode 24 formed on the n-GaN layer 15 exposed by removing a potion of the layered structure; and a transparent p-type electrode 20 formed on the p-GaN layer 19, wherein the p-type electrode 20 is an emission detection surface, and an air layer S is formed between the bottom surface of the u-GaN layer 13 and the concave portions 121.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: April 18, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Toshiya Yokogawa, Kiyoshi Ohnaka, Susumu Koike
  • Publication number: 20060066757
    Abstract: When the main power supply is turned off, the power supply of a video display unit is turned off and the audio signal is muted. At the same time, a time counting unit counts time, and before reaching a predetermined time, a display unit is lighted to notify a quick restart period. In the case where the main power supply is turned on during the predetermined time, the power supply of the video display unit is turned on to cancel the audio mute mode. In the case where the main power is not turned on upon lapse of the predetermined time, the power supply of the receiving unit is also turned off.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 30, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takehiko Numata, Shigero Kamise, Akihiko Ishibashi
  • Publication number: 20050269584
    Abstract: A nitride semiconductor light-emitting device is provided including: a substrate made of a nitride semiconductor; a semiconductor layer made of a nitride semiconductor containing a p-type impurity, the semiconductor layer being formed as contacting an upper surface of the substrate; a first cladding layer made of a nitride semiconductor containing an impurity of a first conductivity type, the first cladding layer being formed on the semiconductor layer; an active layer formed on the first cladding layer; and a second cladding layer made of a nitride semiconductor containing an impurity of a second conductivity type, the second cladding layer being formed on the active layer.
    Type: Application
    Filed: March 21, 2005
    Publication date: December 8, 2005
    Inventors: Yoshiaki Hasegawa, Toshiya Yokogawa, Akihiko Ishibashi
  • Publication number: 20050219423
    Abstract: A television receiver including a liquid crystal display (LCD) panel. When a signal generated by operating a power supply key on a remote controller is received, video and audio are muted, a backlight of the LCD panel is turned off, and a power supply to the LCD panel is turned off. The voltage of the power supply to the LCD panel is monitored. When the voltage is equal to or lower than a predetermined value, the power supply of the whole receiver is turned off. When the power supply key on the remote controller is operated before the voltage supplied to the LCD panel is equal to or lower than the predetermined value, the video and audio mute mode is canceled, the backlight of the LCD panel is turned on, and the power supply to the LCD panel is turned on.
    Type: Application
    Filed: March 29, 2005
    Publication date: October 6, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigero Kamise, Akihiko Ishibashi
  • Patent number: 6940100
    Abstract: A semiconductor light-emitting device of Group III-V compound semiconductors includes a quantum well layer, which is formed over a substrate and includes a barrier layer and a well layer that are alternately stacked one upon the other. The band gap of the well layer is narrower than that of the barrier layer. The well layer contains indium and nitrogen, while the barrier layer contains aluminum and nitrogen. In this structure, a tensile strain is induced in the barrier layer, and therefore, a compressive strain induced in the quantum well layer can be reduced. As a result, a critical thickness, at which pits are created, can be increased.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: September 6, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ayumu Tsujimura, Yoshiaki Hasegawa, Akihiko Ishibashi, Isao Kidoguchi, Yuzaburo Ban, Masakatsu Suzuki
  • Patent number: 6927149
    Abstract: A nitride semiconductor device comprising a substrate (101) having trenches (102b) each formed of a cavity and peaks (102a) formed from a group III nitride on the surface thereof; a nitride semiconductor layer (106) formed on the substrate (101); and a nitride semiconductor multilayered structure that is formed on the nitride semiconductor layer (106) and has an active layer, wherein the lattice constant of the substrate (101) is different from that of the group III nitride substance (102a), the substrate (101) has a mask (104a) formed from a dielectric (104), the mask (104a) is formed only on the side surfaces of the peaks (102a), the upper surfaces of the peaks (102a) are exposed and the substrate (101) is exposed in the trenches (102b), a height L1 of the mask (104a) is not less than 50 nm and not more than 5000 nm, a width L2 of the trench (102b) is not less than 5000 nm and not more than 50000 nm, and an aspect ratio L1/L2 of the trenches (102b) is not less than 0.001 and not more than 1.0.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: August 9, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Gaku Sugahara, Yasutoshi Kawaguchi, Akihiko Ishibashi, Toshiya Yokogawa, Atsushi Matsubara
  • Patent number: 6921678
    Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: July 26, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
  • Publication number: 20050142682
    Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.
    Type: Application
    Filed: February 24, 2005
    Publication date: June 30, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
  • Patent number: 6911351
    Abstract: The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of AluGavInwN, wherein 0?u, v, w?1 and u+v+w=1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of AlxGayInzN, wherein 0?x, y, z?1 and x+y+z=1, by using, as a seed crystal, C planes corresponding to top faces of the convexes exposed from the mask film.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: June 28, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Kidoguchi, Akihiko Ishibashi, Ryoko Miyanaga, Gaku Sugahara, Masakatsu Suzuki, Masahiro Kume, Yuzaburo Ban, Kiyoyuki Morita, Ayumu Tsujimura, Yoshiaki Hasegawa
  • Publication number: 20050116614
    Abstract: A light source of the present invention includes: a semiconductor light emitting device which has a light emitting face and emits light from part of the light emitting face; a container which has a light transmitting window for transmitting the light and accommodates the semiconductor light emitting device; and a gettering portion for performing gettering of a material containing at least one of carbon and silicon. The gettering portion is positioned, in the container, in a region other than the part of the light emitting face of the semiconductor light emitting device.
    Type: Application
    Filed: November 19, 2004
    Publication date: June 2, 2005
    Inventors: Isao Kidoguch, Yasuo Kitaoka, Hiroyoshi Yajima, Keiji Ito, Akihiko Ishibashi, Yoshiaki Hasegawa, Kiminori Mizuuchi