Abstract: A method of producing a resin-sealed package is provided with: providing an electronic component which has a plurality of terminals on one face, a first support member and a second support member; temporarily fixing said electronic component to a surface of said first support member by a first adhesive agent layer, to face said terminals with said first support member; fixing said second support member having a second adhesive agent layer to said electronic component while interposing said electronic component between said first support member and said second support member to face said second adhesive agent layer with a back face side of said electronic component; resin sealing said electronic component between said first support member and said second support member; peeling said first support member and said first adhesive agent layer from said electronic component and a sealing resin; and stacking an insulating resin layer and a wiring layer which is electrically connected to said terminals of said electr

Abstract: A semiconductor device includes a wiring substrate, and a semiconductor chip, wherein the wiring substrate includes a glass plate having an opening portion penetrating through a first surface of the glass plate to a second surface of the glass plate, a resin portion penetrating through the first surface to the second surface, and a through wiring penetrating through the resin portion from the first surface to the second surface to electrically connect a first wiring layer formed on a side of the first surface with a third wiring layer formed on a side of the second surface, wherein the semiconductor chip is accommodated inside the opening portion.

Abstract: A wiring board with lead pins includes: connection pads formed on a wiring board, and lead pins bonded through a conductive material to the connection pads, wherein each of the lead pins has a head portion that is formed in one end of a shaft portion to be larger in diameter than the shaft portion, the head portions are bonded to the connection pads by the conductive material, a face of the wiring board on which the connection pads are formed is resin-sealed by a first resin to be thicker than the head portions, except portions to which the head portions are bonded, and sides of faces of the head portions to which the shaft portions are connected are sealed to be in close contact with the first resin by a second resin.

Abstract: A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.

Abstract: A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

Abstract: According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

Abstract: A disclosed semiconductor device includes a reinforcing board having first and second faces, an electronic part accommodating portion penetrating the reinforcing board, a through hole, an electronic part having a front face on which an electrode pad is formed and a back face, a through electrode installed inside the through hole, a first sealing resin filling a gap between the through electrode and an inner wall of the through hole, a second sealing resin filled into the electronic part accommodating portion while causing the bonding face of the electrode pad of the electronic part accommodating portion to be exposed to an outside, and a multi-layered wiring structure configured to include insulating layers laminated on the first face of the reinforcing board and an interconnection pattern, wherein the interconnection pattern is directly connected to the electrode pad of the electronic part and the through electrode.

Abstract: A method of manufacturing a semiconductor package comprises: preparing a photosensitive insulating material having a first surface and a second surface opposite to the first surface; bonding a semiconductor chip to the first surface of the photosensitive insulating material with a connecting terminal of the semiconductor chip facing the first surface of the photosensitive insulating material; exposing the second surface of the photosensitive insulating material after the bonding the semi-conductor to the first surface of the photosensitive material; encapsulating the first surface of the photosensitive insulating material, and the semiconductor chip bonded to the first surface, with a resin to form a resin encapsulated portion after exposing the second surface of the photosensitive insulating material; and developing the photosensitive insulating material, thereby forming a through-hole communicating with the connecting terminal of the semiconductor chip in the photosensitive insulating material after the exp

Abstract: A semiconductor package of the present invention, includes a wiring substrate, a lead pin fixed to a connection pad on one surface side of the wiring substrate by solder, and a reinforcing resin layer formed on a surface of the wiring substrate on which the lead pin is provided and having a projection-shaped resin portion which projects locally around the lead pin and covers a side surface of a base portion side of the lead pin. The projection-shaped resin portion has a top surface extending from an outer peripheral portion of the lead pin to an outside, and a side surface constituting a non-identical surface to the top surface.

Abstract: A module substrate is provided. The module substrate includes: a core portion; a build-up layer formed on the core portion and including a wiring pattern and an insulating layer; an optical transmission mechanism including: an optical transmission component including an optical waveguide, and a mounting portion on which a semiconductor element is to be mounted. The mounting portion is electrically connected to the optical transmission mechanism via the wiring pattern. The mounting portion includes a first mounting portion and a second mounting portion, and the optical transmission mechanism is disposed between the first mounting portion and the second mounting portion.

Abstract: A wiring board has a structure where multiple wiring layers are stacked one on top of another with insulating layers interposed therebetween. A sheet-shaped member is buried in an outermost insulating layer located on a side of the structure opposite to a side on which a semiconductor element is to be mounted. The sheet-shaped member has a modulus of elasticity and a coefficient of thermal expansion which are similar to a modulus of elasticity and a coefficient of thermal expansion of the semiconductor element. The sheet-shaped member is made of a material having a modulus of elasticity and a coefficient of thermal expansion which are enough to bring respective distributions thereof into a substantially symmetric form in a direction orthogonal to a surface of the wiring board in the case where the semiconductor element is mounted.

Abstract: A manufacturing method includes forming a semi-cured insulation layer made of a photosensitive material on a supporting body; forming an opening part in the insulation layer by a photolithography method, the opening part being configured to expose the supporting body; arranging a semiconductor chip on the insulation layer so that a position of an electrode of the semiconductor chip is consistent with a position of the opening part, and curing the insulation layer; forming sealing resin on a surface of the insulation layer at the semiconductor chip side, the sealing resin being configured to seal the semiconductor chip; removing the supporting body; and providing a wiring layer on a surface of the insulation layer opposite to the semiconductor chip side, the wiring layer being electrically connected to the electrode exposed in the opening part, so that a wiring structural body including the insulation layer and the wiring layer is formed.

Abstract: In a package for a semiconductor device, a core substrate has two metal plates, each of which includes a first through hole, a second through hole, a projection, and an insulating layer formed on its surface. The metal plates are stacked in a manner that the projections of the mutual metal plates enter the second through hole of the metal plate on a partner side, and the first through holes of the metal plates form a through hole penetrating the core substrate. A tip end of each of the projections of the metal plates is exposed to a surface of the metal plate on the partner side to form a first terminal portion, and a second terminal portion is exposed from the insulating layer and formed on a surface of the metal plate on a side where the first terminal portion of the metal plate on the partner side is exposed.

Abstract: A semiconductor element sealed substrate including a semiconductor element covered by an insulating layer is fabricated while a wiring substrate formed by stacking wiring layers is fabricated by a process different from the process of fabricating the semiconductor element sealed substrate. Next, the semiconductor element sealed substrate and the wiring substrate are stacked on each other in such a way that electrode terminals of the semiconductor element and corresponding conductive bumps on the outermost wiring layer face each other. The electrode terminals and the conductive bumps are thus connected to each other.

Abstract: A semiconductor element sealed substrate including a semiconductor element covered by an insulating layer is fabricated while a wiring substrate formed by stacking wiring layers is fabricated by a process different from the process of fabricating the semiconductor element sealed substrate. Next, the semiconductor element sealed substrate and the wiring substrate are stacked on each other in such a way that electrode terminals of the semiconductor element and corresponding conductive bumps on the outermost wiring layer face each other. The electrode terminals and the conductive bumps are thus connected to each other.

Abstract: A manufacturing method includes forming a semi-cured insulation layer made of a photosensitive material on a supporting body; forming an opening part in the insulation layer by a photolithography method, the opening part being configured to expose the supporting body; arranging a semiconductor chip on the insulation layer so that a position of an electrode of the semiconductor chip is consistent with a position of the opening part, and curing the insulation layer; forming sealing resin on a surface of the insulation layer at the semiconductor chip side, the sealing resin being configured to seal the semiconductor chip; removing the supporting body; and providing a wiring layer on a surface of the insulation layer opposite to the semiconductor chip side, the wiring layer being electrically connected to the electrode exposed in the opening part, so that a wiring structural body including the insulation layer and the wiring layer is formed.

Abstract: A semiconductor device includes a semiconductor chip having a connection electrode on a surface side, and a resin substrate sealing a periphery of the semiconductor chip and formed to have a thickness from a back surface of the semiconductor chip to a lower side thereof, and the resin substrate whose lower surface is positioned to a lower side than the back surface of the semiconductor chip. A wiring layer is connected directly to the connection electrode of the semiconductor chip without the intervention of solder.

Abstract: A semiconductor package includes a semiconductor chip; a resin part configured to cover a side surface of the semiconductor chip; and a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip, wherein the resin part is formed so as to cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip.

Abstract: A method of manufacturing a semiconductor package comprises: preparing a photosensitive insulating material having a first surface and a second surface opposite to the first surface; bonding a semiconductor chip to the first surface of the photosensitive insulating material with a connecting terminal of the semiconductor chip facing the first surface of the photosensitive insulating material; exposing the second surface of the photosensitive insulating material after the bonding the semi-conductor to the first surface of the photosensitive material; encapsulating the first surface of the photosensitive insulating material, and the semiconductor chip bonded to the first surface, with a resin to form a resin encapsulated portion after exposing the second surface of the photosensitive insulating material; and developing the photosensitive insulating material, thereby forming a through-hole communicating with the connecting terminal of the semiconductor chip in the photosensitive insulating material after the exp

Abstract: A disclosed semiconductor device includes a reinforcing board having first and second faces, an electronic part accommodating portion penetrating the reinforcing board, a through hole, an electronic part having a front face on which an electrode pad is formed and a back face, a through electrode installed inside the through hole, a first sealing resin filling a gap between the through electrode and an inner wall of the through hole, a second sealing resin filled into the electronic part accommodating portion while causing the bonding face of the electrode pad of the electronic part accommodating portion to be exposed to an outside, and a multi-layered wiring structure configured to include insulating layers laminated on the first face of the reinforcing board and an interconnection pattern, wherein the interconnection pattern is directly connected to the electrode pad of the electronic part and the through electrode.