Patents by Inventor Akihiro Itou

Akihiro Itou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959197
    Abstract: A first aspect of the present invention is carbon fiber wherein the surface of a monofilament has a center line average roughness Ra of 6.0 nm or more and 13 nm or less, and the monofilament has a long diameter/short diameter ratio of 1.11 or more and 1.245 or less. A second aspect of the present invention is carbon fiber precursor acrylic fiber wherein the surface of a monofilament has a center line average roughness Ra of 18 nm or more and 27 nm or less, and the monofilament has a long diameter/short diameter ratio of 1.11 or more and 1.245 or less. The carbon fiber according to the first aspect is obtained by stabilizing and carbonizing under specific conditions the carbon fiber precursor acrylic fiber according to the second aspect.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: April 16, 2024
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Naomasa Matsuyama, Yuutarou Nakamura, Norifumi Hirota, Hiroko Matsumura, Katsuhiko Ikeda, Kouki Wakabayashi, Tadashi Ootani, Akihiro Itou, Kenji Hirano, Akito Hatayama, Kenji Kaneta, Atsushi Nakajima
  • Publication number: 20230420277
    Abstract: Disclosed is a recipe proposal device 10 including: an input section 11 for inputting a target information regarding a target shape of a substrate to be processed in a substrate processing apparatus; a recipe proposal section 12 that proposes a process recipe used in the substrate processing apparatus in order to form the target shape, based on the target information; a calculation section 13 that calculates a prediction information regarding a predicted shape when the substrate is processed in the substrate processing apparatus using the process recipe; and a display section 14 that displays the target information and the prediction information.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 28, 2023
    Inventors: Akihiro ITOU, Hiroshi SHIROUZU, Atsushi HARIKAI
  • Patent number: 11830758
    Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: November 28, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou
  • Patent number: 11817323
    Abstract: An etching method including: a preparation step of preparing a resin layer and an electronic component supported thereby; and a resin etching step of etching the resin layer. The electronic component has a first surface covered with a protective film, a second surface opposite thereto, and a sidewall therebetween. The second surface is facing the resin layer. The resin layer is larger than the electronic component when seen from the first surface side. The resin etching step includes: a deposition step of depositing a first film, using a first plasma, on a surface of the protective film and a surface of the resin layer; and a removal step of removing, using a second plasma, the first film deposited on the resin layer and at least part of the resin layer. The deposition and removal steps are alternately repeated, with the protective film allowed to continue to exist.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: November 14, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Patent number: 11688641
    Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 27, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Hidehiko Karasaki, Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Publication number: 20230102635
    Abstract: An electronic component cleaning method including: a preparation step of preparing an electronic component having a first surface covered with a protective film, a second surface opposite to the first surface, a sidewall between the first and second surfaces, and an adhering matter adhering to the sidewall; and a sidewall cleaning step of cleaning the sidewall. The sidewall cleaning step includes a deposition step of depositing a first film on the protective film and a surface of the adhering matter, using a first plasma, and a removal step of removing the first film deposited on the surface of the adhering matter, together with at least part of the adhering matter, using a second plasma. In the sidewall cleaning step, the deposition step and the removal step are alternately repeated a plurality of times, so as to allow the protective film to continue to exist.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 30, 2023
    Inventors: Shogo OKITA, Akihiro ITOU, Atsushi HARIKAI
  • Publication number: 20220402072
    Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer, the substrate having element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and a step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step includes a step of irradiating a first laser beam having a first pulse width, to remove the wiring layer in an edge portion of the dicing region, and a step of irradiating a second laser beam having a second pulse width which is longer than the first pulse width, to remove the wiring layer inside from the edge portion.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 22, 2022
    Inventors: Hidefumi SAEKI, Hidehiko KARASAKI, Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
  • Publication number: 20220181209
    Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 9, 2022
    Inventors: Atsushi HARIKAI, Shogo OKITA, Akihiro ITOU, Toshiyuki TAKASAKI
  • Publication number: 20220181188
    Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 9, 2022
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou
  • Publication number: 20220165577
    Abstract: A plasma processing method including: exposing to a first plasma a substrate having a compound semiconductor layer and a mask partially covering a surface of the compound semiconductor layer, to form a protective film at least on the bottom of a groove formed in a region where the compound semiconductor layer is not covered with the mask; removing the protective film at the bottom by exposing the substrate to a second plasma, to expose the compound semiconductor layer; and removing the conductive semiconductor layer exposed at the bottom of the groove by exposing the substrate to a third plasma generated from a gas containing chlorine and/or bromine, while allowing a reaction product between the compound semiconductor layer and the third plasma to accumulate on an upper portion of the groove. The reaction product is removed by applying a high-frequency power to a stage on which the substrate is placed.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 26, 2022
    Inventors: Toshiyuki TAKASAKI, Shogo OKITA, Akihiro ITOU, Atsushi HARIKAI
  • Patent number: 11335564
    Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: May 17, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Toshiyuki Takasaki, Shogo Okita
  • Patent number: 11219929
    Abstract: An element chip cleaning method including: an element chip preparation step of preparing at least one element chip having a first surface and a second surface opposite the first surface, the first surface covered with a resin film; a first cleaning step of bringing a first cleaning liquid into contact with the resin film, the first cleaning liquid including a solvent that dissolves at least part of a resin component contained in the resin film; and a second cleaning step of spraying a second cleaning liquid against the resin film from the first surface side of the element chip, after the first cleaning step.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: January 11, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Toshiyuki Takasaki, Hidefumi Saeki, Shogo Okita
  • Patent number: 11211178
    Abstract: Provided is a neutron shielding material having excellent transparency and high neutron shielding ability. In this neutron shielding material, light transmittance at wave length of 400 to 700 nm is 80% or greater, and the thickness of a 1/10 value layer of a neutron generated from Californium 252 is 14 cm or less.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 28, 2021
    Assignees: MITSUBISHI CHEMICAL CORPORATION, CO. LTD. RSC
    Inventors: Yuusuke Watanabe, Akihiro Itou, Takaya Shinmura, Teruo Hashimoto, Takaaki Kishimoto
  • Patent number: 11189480
    Abstract: An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: November 30, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Publication number: 20210287913
    Abstract: An etching method including: a preparation step of preparing a resin layer and an electronic component supported thereby; and a resin etching step of etching the resin layer. The electronic component has a first surface covered with a protective film, a second surface opposite thereto, and a sidewall therebetween. The second surface is facing the resin layer. The resin layer is larger than the electronic component when seen from the first surface side. The resin etching step includes: a deposition step of depositing a first film, using a first plasma, on a surface of the protective film and a surface of the resin layer; and a removal step of removing, using a second plasma, the first film deposited on the resin layer and at least part of the resin layer. The deposition and removal steps are alternately repeated, with the protective film allowed to continue to exist.
    Type: Application
    Filed: March 1, 2021
    Publication date: September 16, 2021
    Inventors: Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
  • Patent number: 10964597
    Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 30, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Hidefumi Saeki, Akihiro Itou
  • Publication number: 20210057227
    Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 25, 2021
    Inventors: Akihiro ITOU, Atsushi HARIKAI, Toshiyuki TAKASAKI, Shogo OKITA
  • Patent number: 10923357
    Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step, a setting step for setting the substrate on a stage, and a plasma-dicing step for dividing the substrate into a plurality of element chips, wherein the plasma-dicing step is achieved by repeatedly implementing etching routines each including an etching step for etching the second layer along the street regions to form a plurality of grooves and a depositing step for depositing a protective film on inner walls of the grooves, wherein the plasma-dicing step includes a first etching step for forming the grooves each having a first scallop on the inner wall thereof at a first pitch, and a second etching step for forming the grooves each having a second scallop on the inner wall thereof at a second pitch, and wherein the second pitch is greater than the first pitch.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 16, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Noriyuki Matsubara, Shogo Okita
  • Patent number: 10892190
    Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including dicing regions and element regions, attaching a holding sheet held on a frame with a die attach film in between, forming a protective film covering the substrate, forming a plurality of grooves in the protective film along the dicing regions, plasma-etching the substrate to expose the die attach film and then die attach film along the dicing regions, and picking up each of the element chips along with the separated die attach film away from the holding sheet, wherein the die attach film has an area greater than that of the substrate, and wherein the protective film includes a first covering portion covering the substrate and a second covering portion covering at least a portion of the die attach film that extends beyond an outer edge of the substrate.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: January 12, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Noriyuki Matsubara, Hidefumi Saeki, Akihiro Itou
  • Publication number: 20200406308
    Abstract: An element chip cleaning method including: an element chip preparation step of preparing at least one element chip having a first surface and a second surface opposite the first surface, the first surface covered with a resin film; a first cleaning step of bringing a first cleaning liquid into contact with the resin film, the first cleaning liquid including a solvent that dissolves at least part of a resin component contained in the resin film; and a second cleaning step of spraying a second cleaning liquid against the resin film from the first surface side of the element chip, after the first cleaning step.
    Type: Application
    Filed: June 9, 2020
    Publication date: December 31, 2020
    Inventors: Akihiro ITOU, Atsushi HARIKAI, Toshiyuki TAKASAKI, Hidefumi SAEKI, Shogo OKITA