Patents by Inventor Akihiro Oda

Akihiro Oda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200185866
    Abstract: Provided is an electrical connection box into which a greater number of fuses can be inserted without increasing its size. An electrical connection box for a vehicle includes: an insertion housing into which multiple fuses are to be inserted through an open port on one side; multiple fuse terminals for connecting the fuses in the insertion housing to a substrate; a plate-shaped holding member that opposes the insertion housing from a side opposite to the one side of the insertion housing, and holds the multiple fuse terminals; and a case member that includes a flat plate portion for covering the multiple fuse terminals and has a notch that is formed in the covering portion, the holding member being arranged inside of the notch.
    Type: Application
    Filed: November 22, 2019
    Publication date: June 11, 2020
    Inventors: Noriko Okamoto, Akihiro Oda, Masakazu Okumura, Ryoma Hamada, Tatsuya Daidoji
  • Publication number: 20200185182
    Abstract: Provided is an electrical connection box in which a greater number of fuses can be inserted while suppressing an increase in size. An electrical connection box for a vehicle includes: an insertion housing that has a rectangular open port on one side and in which a plurality of rectangular insertion holes into which fuses are to be respectively inserted are provided facing the open port; a first insertion hole row in which a plurality of the insertion holes are provided side by side in a lengthwise direction of the open port, with long sides of the insertion holes adjacent to each other; and a second insertion hole row in which a plurality of the insertion holes are provided side by side in the lengthwise direction of the open port, with short sides of the insertion holes adjacent to each other.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 11, 2020
    Inventors: Noriko Okamoto, Akihiro Oda, Masakazu Okumura, Ryoma Hamada, Tatsuya Daidoji
  • Publication number: 20200185870
    Abstract: Provided is an electrical connection box according to which it is possible to suppress the occurrence of mistakes in a manufacturing process, and it is possible to reliably prevent the occurrence of faulty products. The electrical connection box to be used in a vehicle includes a terminal having an inner-fitting plate portion that is fit into and held in a slit of a holding member; and multiple substrate connection portions that protrude along a surface of the inner-fitting plate portion from one side edge of the inner-fitting plate portion. The terminal has a shape that is asymmetrical in a direction in which the multiple substrate connection portions are arranged side by side.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 11, 2020
    Inventors: Ryoma Hamada, Akihiro Oda, Masakazu Okumura, Tatsuya Daidoji, Noriko Okamoto
  • Publication number: 20200152802
    Abstract: An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer.
    Type: Application
    Filed: June 4, 2018
    Publication date: May 14, 2020
    Inventors: Yujiro TAKEDA, Hiroshi MATSUKIZONO, Akihiro ODA, Shogo MURASHIGE, Kohhei TANAKA
  • Patent number: 10571761
    Abstract: An active matrix substrate includes a demultiplexer circuit which includes a plurality of DMX circuit TFTs. Each of the DMX circuit TFTs includes a front-gate electrode (FG) supplied with a control signal from one of a plurality of control signal main lines ASW, BSW and a back-gate electrode (BG) supplied with a back-gate signal which is different from the control signal. The plurality of DMX circuit TFTs includes first DMX circuit TFTs (T1a, T1b) and second DMX circuit TFTs (T2a, T2b). The back-gate electrode of each of the first DMX circuit TFTs (T1a, T1b)is connected with a first back-gate signal main line (BGL(1)) which supplies a first back-gate signal and, the back-gate electrode of each of the second DMX circuit TFTs (T2a, T2b)is connected with a second back-gate signal main line (BGL(2)) which supplies a second back-gate signal which is different from the first back-gate signal.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Yamamoto, Akihiro Oda, Tadayoshi Miyamoto
  • Patent number: 10462914
    Abstract: A cover structure that includes a base that is attached to a circuit substrate of an electric connection box on which an electrical component is mounted, the base being used as a receptacle for a cable that is to be electrically connected to the electrical component; and a housing that houses the circuit substrate.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 29, 2019
    Assignee: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Masakazu Okumura, Akihiro Oda, Tatsuya Daidoji, Ryoma Hamada, Noriko Okamoto
  • Publication number: 20190131459
    Abstract: A gate driver TFT 30 includes: a gate electrode 30a; a channel portion 30d overlapping the gate electrode 30a with a gate insulating film 16 disposed therebetween and constructed from an oxide semiconductor film 17 that is a semiconductor film; a source electrode 30b connected to one end of the channel portion 30d; a drain electrode 30c connected to another end of the channel portion 30d; and an intermediate electrode 22 connected to the channel portion 30d at a position at which a distance L1 to the drain electrode 30c is greater than a distance L2 to the source electrode 30b.
    Type: Application
    Filed: April 7, 2017
    Publication date: May 2, 2019
    Inventors: Tadayoshi MIYAMOTO, Akihiro ODA
  • Publication number: 20190124779
    Abstract: A cover structure that includes a base that is attached to a circuit substrate of an electric connection box on which an electrical component is mounted, the base being used as a receptacle for a cable that is to be electrically connected to the electrical component; and a housing that houses the circuit substrate.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 25, 2019
    Applicant: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Masakazu OKUMURA, Akihiro ODA, Tatsuya DAIDOJI, Ryoma HAMADA, Noriko OKAMOTO
  • Publication number: 20190079330
    Abstract: An active matrix substrate includes a demultiplexer circuit which includes a plurality of DMX circuit TFTs. Each of the DMX circuit TFTs includes a front-gate electrode (FG) supplied with a control signal from one of a plurality of control signal main lines ASW, BSW and a back-gate electrode (BG) supplied with a back-gate signal which is different from the control signal. The plurality of DMX circuit TFTs includes first DMX circuit TFTs (T1a, T1b) and second DMX circuit TFTs (T2a, T2b). The back-gate electrode of each of the first DMX circuit TFTs (T1a, T1b)is connected with a first back-gate signal main line (BGL(1)) which supplies a first back-gate signal and, the back-gate electrode of each of the second DMX circuit TFTs (T2a, T2b)is connected with a second back-gate signal main line (BGL(2)) which supplies a second back-gate signal which is different from the first back-gate signal.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 14, 2019
    Inventors: Kaoru YAMAMOTO, Akihiro ODA, Tadayoshi MIYAMOTO
  • Patent number: 10158027
    Abstract: A semiconductor device (100) includes a thin film transistor (5) provided on a substrate and including a gate electrode (12), a gate insulating layer (20) in contact with the gate electrode, an oxide semiconductor layer (18) located so as to partially overlap the gate electrode with the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a source electrode (14), and a drain electrode (16). The oxide semiconductor layer (18) includes a gate facing region (18g) overlapping the gate electrode as seen in a direction of normal to the substrate; and offset regions (18os, 18od) provided adjacent to the gate facing region, the offset regions not overlapping the gate electrode, the source electrode or the drain electrode as seen in the direction of normal to the substrate. The gate facing region has a carrier concentration in the range of 1×1017/cm3 or greater and 1×1019/cm3 or less.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: December 18, 2018
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Akihiro Oda
  • Publication number: 20180356660
    Abstract: A plurality of TFTs provided in a peripheral circuit region of an active matrix substrate of an embodiment includes a TFT (10A) in which, when viewed in a direction perpendicular to a substrate (11A), the length in the channel width direction of an oxide semiconductor layer (14A), WAos, is smaller than the length in the channel width direction of a gate electrode (12A), WAg, the length in the channel width direction of a source electrode region (15AR) in which the source electrode (15A) is in contact with the oxide semiconductor layer (14A), WAs, is smaller than the length in the channel width direction of the oxide semiconductor layer (14A), WAos, and the drain electrode (16A) is in contact with the oxide semiconductor layer (14A) in a plurality of drain electrode regions (16AR) arranged in the channel width direction, and the overall length in the channel width direction of the plurality of drain electrode regions (16AR), WAd, is smaller than the length in the channel width direction of the oxide semiconduc
    Type: Application
    Filed: December 2, 2016
    Publication date: December 13, 2018
    Inventors: Masahiro TOMIDA, Akihiro ODA
  • Patent number: 10091882
    Abstract: Provided is a circuit structure using a printed-circuit board with a novel structure that can provide a plurality of types of circuit specifications by switching connection of circuit patterns, allows circuit specifications to be easily identified, and achieves excellent connection workability and connection stability for circuit patterns. The circuit structure includes: a printed-circuit board 18 on which a plurality of circuit patterns are provided; and a circuit switching component, wherein the circuit switching component includes bus bar support bases on which any connection bus bars selected can be mounted and held, the plurality of types of connection bus bars are classified according to the number and the position of lead portions to be electrically connected to connection points, and a plurality of types of circuit specifications are provided by changing a mounting mode of the connection bus bars to the bus bar support bases.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: October 2, 2018
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Masakazu Okumura, Akihiro Oda, Tatsuya Daidoji, Ryoma Hamada, Noriko Okamoto
  • Publication number: 20180160537
    Abstract: Provided is a circuit structure using a printed-circuit board with a novel structure that can provide a plurality of types of circuit specifications by switching connection of circuit patterns, allows circuit specifications to be easily identified, and achieves excellent connection workability and connection stability for circuit patterns. The circuit structure includes: a printed-circuit board 18 on which a plurality of circuit patterns are provided; and a circuit switching component, wherein the circuit switching component includes bus bar support bases on which any connection bus bars selected can be mounted and held, the plurality of types of connection bus bars are classified according to the number and the position of lead portions to be electrically connected to connection points, and a plurality of types of circuit specifications are provided by changing a mounting mode of the connection bus bars to the bus bar support bases.
    Type: Application
    Filed: November 14, 2017
    Publication date: June 7, 2018
    Applicant: Sumitomo Wiring Systems, Ltd.
    Inventors: Masakazu Okumura, Akihiro Oda, Tatsuya Daidoji, Ryoma Hamada, Noriko Okamoto
  • Patent number: 9972935
    Abstract: Provided is a drainage structure for an electrical connection box capable of preventing an internal circuit board from getting wet even if water has entered. An electrical connection box main body is mounted on a vehicle wherein a main body-side connector is located on an upper side and protrudes from an opening in a horizontal direction, and a protruding end portion of a housing peripheral wall of a lateral electrical component attaching portion protrudes to the outside from a lateral window, the lateral electrical component attaching portion protrudes laterally from on a side edge portion of a circuit board. A first drainage channel is provided inside the electrical connection box main body, and a second drainage channel extends downward and having an upper end portion connected to the first drainage channel in the protruding end portion of the housing peripheral wall of the lateral electrical component attaching portion.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: May 15, 2018
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Akihiro Oda, Tatsuya Daidoji, Ryoma Hamada
  • Patent number: 9966040
    Abstract: A display device includes: a display unit, a driver unit, and a control unit. The display unit includes a plurality of pixel units arranged in a matrix. The driver unit includes an output transistor configured to drive a plurality of scanning lines connected to the plurality of pixel units. The control unit is configured to supply to the driver unit in a display period, a signal for displaying an image on the display unit, and control a bias state of the output transistor in a display suspension period, so that an absolute value of a threshold voltage of the output transistor which is increased in the display period decreases.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 8, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Yamamoto, Yasuyuki Ogawa, Akihiro Oda, Masahiro Tomida
  • Patent number: 9905311
    Abstract: A shift register circuit has a plurality of unit circuits that are cascade-connected to one another and that output received pulse signals as output signals in accordance with a clock signal, the shift register circuit sequentially outputting the output signals from the plurality of respective unit circuits. The output circuits each include a double-gate transistor having first gate electrode that controls conductivity between the drain electrode and the source electrode, and a second gate electrode formed through an insulating layer and disposed to face the first gate electrode across a semiconductor layer between the drain electrode and the source electrode. The shift register circuit applies a prescribed voltage to the second gate electrode in accordance with a voltage applied to the first gate electrode.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: February 27, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasuyuki Ogawa, Kaoru Yamamoto, Akihiro Oda, Masahiro Tomida
  • Publication number: 20180013230
    Abstract: Provided is a drainage structure for an electrical connection box capable of preventing an internal circuit board from getting wet even if water has entered. An electrical connection box main body is mounted on a vehicle wherein a main body-side connector is located on an upper side and protrudes from an opening in a horizontal direction, and a protruding end portion of a housing peripheral wall of a lateral electrical component attaching portion protrudes to the outside from a lateral window, the lateral electrical component attaching portion protrudes laterally from on a side edge portion of a circuit board. A first drainage channel is provided inside the electrical connection box main body, and a second drainage channel extends downward and having an upper end portion connected to the first drainage channel in the protruding end portion of the housing peripheral wall of the lateral electrical component attaching portion.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 11, 2018
    Inventors: Akihiro Oda, Tatsuya Daidoji, Ryoma Hamada
  • Publication number: 20170200827
    Abstract: A semiconductor device (100) includes a thin film transistor (5) provided on a substrate and including a gate electrode (12), a gate insulating layer (20) in contact with the gate electrode, an oxide semiconductor layer (18) located so as to partially overlap the gate electrode with the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a source electrode (14), and a drain electrode (16). The oxide semiconductor layer (18) includes a gate facing region (18g) overlapping the gate electrode as seen in a direction of normal to the substrate; and offset regions (18os, 18od) provided adjacent to the gate facing region, the offset regions not overlapping the gate electrode, the source electrode or the drain electrode as seen in the direction of normal to the substrate. The gate facing region has a carrier concentration in the range of 1×1017/cm3 or greater and 1×1019/cm3 or less.
    Type: Application
    Filed: May 28, 2015
    Publication date: July 13, 2017
    Inventor: Akihiro ODA
  • Patent number: 9456510
    Abstract: An electrical junction box (10) has a main body-side connector (40) provided in a box body (12). An attachment body-side connector (76) is provided in an attachment body (14) that is separate from the box body (12) and is connected to the main body-side connector (40) by rotating the attachment body (14) on a rotating portion (72) provided at an end of the attachment body (14). The rotating portion (72) is supported by a support (30) on a side of the box body (12) opposite to the main body-side connector (40), and a positioning portion directly positions the main body-side connector (40) with respect to the upper case (20).
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: September 27, 2016
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Yuuichi Hattori, Akihiro Oda
  • Publication number: 20160190181
    Abstract: A semiconductor device includes: a plurality of thin film transistors including a gate electrode, a gate dielectric layer, a semiconductor layer formed on the gate dielectric layer, and a source electrode and a drain electrode provided on the semiconductor layer; a source metal layer including a global line which supplies a common signal to the plurality of thin film transistors, the global line being made of the same electrically conductive film as the source electrode and drain electrode; and a dielectric protection layer covering the plurality of thin film transistors and the source metal layer. The source metal layer includes a lower layer and an upper layer stacked on a portion of the lower layer. The global line has a first layer structure including the lower layer and the upper layer, and at least a portion of each source electrode and of each drain electrode that is located on the semiconductor layer has a second layer structure including the lower layer but not including the upper layer.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 30, 2016
    Inventors: Naoki UEDA, Akihiro ODA, Hirohiko NISHIKI, Tohru OKABE