Patents by Inventor Akihisa Fujimoto

Akihisa Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system in which extended function can easily be set
    Patent number: 8930613
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device, a controller, an extended function section, and an extension register. The controller controls the nonvolatile semiconductor memory device. The extended function section is controlled by the controller. The extension register which is provided with a certain block length capable of defining an extended function of the extended function section. The controller processes a first command to write header data of a command to operate the extended function section to the extended function section through the extension register, and a second command to read header data of a response from the extended function section through the extension register.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Matsukawa, Akihisa Fujimoto
  • Memory system in which extended function can easily be set
    Patent number: 8904094
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device, a controller, an extended function section, and an extension register. The controller controls the nonvolatile semiconductor memory device. The extended function section is controlled by the controller. The extension register which is provided with a certain block length capable of defining an extended function of the extended function section. The controller processes a first command to write header data of a command to operate the extended function section to the extended function section through the extension register, and a second command to read header data of a response from the extended function section through the extension register.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Matsukawa, Akihisa Fujimoto
  • CARD AND HOST DEVICE
    Publication number: 20140351514
    Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Akihisa FUJIMOTO
  • MEMORY DEVICE, HOST DEVICE, AND SAMPLING CLOCK ADJUSTING METHOD
    Publication number: 20140351499
    Abstract: A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akihisa FUJIMOTO
  • STORAGE DEVICE INCLUDING FLASH MEMORY AND CAPABLE OF PREDICTING STORAGE DEVICE PERFORMANCE BASED ON PERFORMANCE PARAMETERS
    Publication number: 20140337567
    Abstract: A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.
    Type: Application
    Filed: July 29, 2014
    Publication date: November 13, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Akihisa FUJIMOTO
  • MEMORY SYSTEM HAVING HIGH DATA TRANSFER EFFICIENCY AND HOST CONTROLLER
    Publication number: 20140337542
    Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.
    Type: Application
    Filed: July 22, 2014
    Publication date: November 13, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Akihisa FUJIMOTO
  • Memory system capable of increasing data transfer efficiency
    Patent number: 8874989
    Abstract: According to one embodiment, a host controller includes a command generator and detector. The command generator generates a command having a retransmission flag in an argument, and transmits the generated command to a memory device. The detector detects timeout if a response from the memory device cannot be recognized within a defined time. When transmitting an initial command, the host controller clears the retransmission flag and transmits the command. If the detector detects timeout, the host controller sets the retransmission flag, and retransmits the same command as the initial command to the device. If a normal response corresponding to the initial command or retransmitted command is received, the host controller recognizes that the command is correctly executed.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • CARD AND HOST APPARATUS
    Publication number: 20140310460
    Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akihisa FUJIMOTO
  • MEMORY DEVICE, HOST DEVICE, MEMORY SYSTEM, MEMORY DEVICE CONTROL METHOD, HOST DEVICE CONTROL METHOD AND MEMORY SYSTEM CONTROL METHOD
    Publication number: 20140304533
    Abstract: A memory card 100 having a NAND type flash memory connectable to a host device 200, capable of transmitting/receiving a signal to/from the host device 200 at a first voltage (3.3 V) or a second voltage (1.8 V) and safely changing a signal voltage of a transmission/reception signal that mutually checks a signal voltage through handshake processing with the host device 200 when the signal voltage is switched.
    Type: Application
    Filed: June 23, 2014
    Publication date: October 9, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akihisa FUJIMOTO
  • MEMORY SYSTEM IN WHICH EXTENSION FUNCTION CAN EASILY BE SET
    Publication number: 20140297932
    Abstract: According to one embodiment, a non-transitory medium, a controller, a memory, an extension function section, and an extension register. The controller controls the non-transitory medium. The memory which is serving as a work area is connected to the controller. The extension function section is controlled by the controller. The extension register which is provided on the memory is provided with a certain block length capable of defining an extension function of the extension function section. The controller processes a first command to write header data of a command to operate the extension function section to the extension function section through the extension register, and a second command to read header data of a response from the extension function section through the extension register.
    Type: Application
    Filed: June 10, 2014
    Publication date: October 2, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinichi MATSUKAWA, Akihisa Fujimoto
  • Method for determining transmission error due to a crosstalk between signal lines by comparing tuning pattern signals sent in parallel from a memory device with the tuning pattern signals pre-stored in a host device
    Patent number: 8839021
    Abstract: A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Card and host device
    Patent number: 8827167
    Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Storage device including flash memory and capable of predicting storage device performance based on performance parameters
    Patent number: 8832361
    Abstract: A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Memory system having high data transfer efficiency and host controller
    Patent number: 8825923
    Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Card and host apparatus
    Patent number: 8812745
    Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Memory device, host device, memory system, memory device control method, host device control method and memory system control method
    Patent number: 8799689
    Abstract: A memory card 100 having a NAND type flash memory connectable to a host device 200, capable of transmitting/receiving a signal to/from the host device 200 at a first voltage (3.3 V) or a second voltage (1.8 V) and safely changing a signal voltage of a transmission/reception signal that mutually checks a signal voltage through handshake processing with the host device 200 when the signal voltage is switched.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 5, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Memory system in which extension function can easily be set
    Patent number: 8775724
    Abstract: According to one embodiment, a non-transitory medium, a controller, a memory, an extension function section, and an extension register. The controller controls the non-transitory medium. The memory which is serving as a work area is connected to the controller. The extension function section is controlled by the controller. The extension register which is provided on the memory is provided with a certain block length capable of defining an extension function of the extension function section. The controller processes a first command to write header data of a command to operate the extension function section to the extension function section through the extension register, and a second command to read header data of a response from the extension function section through the extension register.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Matsukawa, Akihisa Fujimoto
  • MEMORY SYSTEM HAVING HIGH DATA TRANSFER EFFICIENCY AND HOST CONTROLLER
    Publication number: 20140156881
    Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.
    Type: Application
    Filed: February 5, 2014
    Publication date: June 5, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Akihisa FUJIMOTO
  • CARD AND HOST APPARATUS
    Publication number: 20140149667
    Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.
    Type: Application
    Filed: January 30, 2014
    Publication date: May 29, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akihisa FUJIMOTO
  • Memory system having high data transfer efficiency and host controller
    Patent number: 8683093
    Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto