Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Abstract: A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.

Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Abstract: A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.

Abstract: A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.

Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.

Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.

Abstract: A memory card includes a clock I/O circuit, a data I/O circuit, a delay element, and an adjustment value holding circuit. The clock input/output circuit receives a first clock from a host apparatus. The data I/O circuit receives a second clock from the host apparatus in a write timing adjustment mode. The data I/O circuit transmits and receives data to and from the host apparatus in a data transfer mode. In the write timing adjustment mode, the delay element adjusts a phase of the second clock in accordance with the first clock so as to receive the data received in the data transfer mode in response to the first clock. The adjustment value holding circuit holds an adjustment value for the phase of the second clock adjusted. In the data transfer mode, the delay element adjusts a phase of the data in accordance with the adjustment value.

Abstract: A data updating method, a memory system and a memory device in which the memory device is connectable to a host device and has a memory section and a memory controller, the memory section consists of a first memory section which can be divided into partitions having multiple different attributes, and a work space which is managed by the memory controller, and the method of updating data which is stored in the memory device uses one of the writing methods which has been selected from among multiple different writing methods of writing data into the partition, depending on the attribute of the partition, to perform an updating process, and can securely update the data.

Abstract: A memory card 100 having a NAND type flash memory connectable to a host device 200, capable of transmitting/receiving a signal to/from the host device 200 at a first voltage (3.3 V) or a second voltage (1.8 V) and safely changing a signal voltage of a transmission/reception signal that mutually checks a signal voltage through handshake processing with the host device 200 when the signal voltage is switched.

Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.

Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Abstract: A memory card includes a clock I/O circuit, a data I/O circuit, a delay element, and an adjustment value holding circuit. The clock input/output circuit receives a first clock from a host apparatus. The data I/O circuit receives a second clock from the host apparatus in a write timing adjustment mode. The data I/O circuit transmits and receives data to and from the host apparatus in a data transfer mode. In the write timing adjustment mode, the delay element adjusts a phase of the second clock in accordance with the first clock so as to receive the data received in the data transfer mode in response to the first clock. The adjustment value holding circuit holds an adjustment value for the phase of the second clock adjusted. In the data transfer mode, the delay element adjusts a phase of the data in accordance with the adjustment value.

Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.

Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Abstract: A memory device (11) includes a semiconductor memory (11c) and a controller (11a). The semiconductor memory (11c) includes a first storage area (11c1) and a second storage area (11c2). The controller (11a) controls the semiconductor m (11c). The memory device (11) is capable of having a first state which is accessible to the first storage area (11c1) and a sec state in which data is readable from the second storage area (11c2). The controller (11a) is configured to recognize a first command, a second command, and a third command. The first command transfers the memory device (11) to the first state after the memory device is turned on. The second command transfers the memory device (11) from the first state to the second state. The third command transfers the memory device (11) to the second state without passing through the first state after the memory device is turned on.

Abstract: A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.

Abstract: A recordable memory device includes a nonvolatile semiconductor memory, and a controller controlling the nonvolatile semiconductor memory based on a recordable system. The nonvolatile semiconductor memory has a user area capable of directly making an access from a host, and a system area managed by the controller. A data writing to the reformatted user area of the nonvolatile semiconductor memory executes from a start point which is an unused area after the final physical address of old recordable data recorded in the user area before the reformat. The data writing executes from a start point which is a top physical address in the user area, when the start point exceeds the final physical address in the user area.

Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.