Patents by Inventor Akihisa Fujimoto

Akihisa Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8447896
    Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: May 21, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Patent number: 8423679
    Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Patent number: 8397990
    Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Publication number: 20130060995
    Abstract: A memory card 100 having a NAND type flash memory connectable to a host device 200, capable of transmitting/receiving a signal to/from the host device 200 at a first voltage (3.3 V) or a second voltage (1.8 V) and safely changing a signal voltage of a transmission/reception signal that mutually checks a signal voltage through handshake processing with the host device 200 when the signal voltage is switched.
    Type: Application
    Filed: November 2, 2012
    Publication date: March 7, 2013
    Inventor: Akihisa FUJIMOTO
  • Publication number: 20130019119
    Abstract: A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 17, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akihisa FUJIMOTO
  • Publication number: 20130013882
    Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Inventor: Akihisa FUJIMOTO
  • Patent number: 8321697
    Abstract: A memory card 100 having a NAND type flash memory connectable to a host device 200, capable of transmitting/receiving a signal to/from the host device 200 at a first voltage (3.3 V) or a second voltage (1.8 V) and safely changing a signal voltage of a transmission/reception signal that mutually checks a signal voltage through handshake processing with the host device 200 when the signal voltage is switched.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: November 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Patent number: 8286874
    Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: October 16, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Publication number: 20120260001
    Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.
    Type: Application
    Filed: June 19, 2012
    Publication date: October 11, 2012
    Inventors: Kosei Okamoto, Hiroyuki Sakamoto, Akihisa Fujimoto, Masao Suga
  • Patent number: 8286024
    Abstract: A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: October 9, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Publication number: 20120254600
    Abstract: According to one embodiment of the present disclosure, a semiconductor system may be disclosed. The semiconductor system according to the one embodiment may include, for example, a plurality of electronic devices and a host apparatus. The host apparatus may simultaneously initialize the plurality of electronic devices in units of group.
    Type: Application
    Filed: December 17, 2010
    Publication date: October 4, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akihisa Fujimoto
  • Publication number: 20120254524
    Abstract: A controller has a random write mode and a sequential write mode to which it transitions when receiving a start command. The controller in the sequential write mode identifies a data stream partially formed by a data item through a control command or a logical address. It also prepares free unit areas for respective data streams, and writes data items in successive storage areas in a corresponding unit area in an order identical to addresses of the data items. When the controller receives an end command, it performs end processing on a unit area for a corresponding data stream. The controller in the sequential write mode transitions to the random write mode when completing the end processing to all data streams or detects a random write request.
    Type: Application
    Filed: June 15, 2012
    Publication date: October 4, 2012
    Inventor: Akihisa FUJIMOTO
  • Publication number: 20120226830
    Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.
    Type: Application
    Filed: May 16, 2012
    Publication date: September 6, 2012
    Inventor: Akihisa FUJIMOTO
  • Publication number: 20120177050
    Abstract: According to one embodiment, a semiconductor device includes a device. The device includes a decoder, a generation circuit, a register, and a modifier. The decoder analyzes a command of a received packet. The generation circuit generates a unique device number in accordance with information in the packet. The register holds the generated unique device number. The modifier updates and outputs the packet. When a packet issued by a host is a command packet, among broadcast packets which return to the host through one or more devices, for determining the unique device number, the command packet includes parameters of an initial value and final value of device number.
    Type: Application
    Filed: March 20, 2012
    Publication date: July 12, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akihisa FUJIMOTO
  • Publication number: 20120176855
    Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.
    Type: Application
    Filed: March 16, 2012
    Publication date: July 12, 2012
    Inventor: Akihisa FUJIMOTO
  • Patent number: 8219733
    Abstract: When initializing a device, an operation mode of the device is acquired and stored by a predetermined procedure using a predetermined pin. In response to a command, the device executes a signal assignment on a plurality of data pins peculiar to an operation mode indicated by the received command, thereby switching a data transfer width, and allowing the device to operate in the operation mode designated by the received command.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosei Okamoto, Hiroyuki Sakamoto, Akihisa Fujimoto, Masao Suga
  • Patent number: 8195845
    Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Patent number: 8162216
    Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: April 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Publication number: 20120079338
    Abstract: According to one embodiment, a host controller includes a command generator and detector. The command generator generates a command having a retransmission flag in an argument, and transmits the generated command to a memory device. The detector detects timeout if a response from the memory device cannot be recognized within a defined time. When transmitting an initial command, the host controller clears the retransmission flag and transmits the command. If the detector detects timeout, the host controller sets the retransmission flag, and retransmits the same command as the initial command to the device. If a normal response corresponding to the initial command or retransmitted command is received, the host controller recognizes that the command is correctly executed.
    Type: Application
    Filed: March 17, 2011
    Publication date: March 29, 2012
    Inventor: Akihisa FUJIMOTO
  • Publication number: 20120072618
    Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.
    Type: Application
    Filed: March 21, 2011
    Publication date: March 22, 2012
    Inventor: Akihisa FUJIMOTO