Abstract: A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, a gate insulating film, gate electrodes, first electrodes, a second electrode, and a gate pad portion configured by a gate electrode pad and a connecting portion. The second semiconductor layer includes a first region facing the connecting portion and a second region facing a corner portion of the gate electrode pad, and the first and second regions are free of the second semiconductor regions. The oxide film is provided on surfaces of the second semiconductor regions and the first and second regions, and the oxide film and the gate insulating film are made of a same material.

Abstract: A silicon carbide semiconductor device includes: a drift layer provided over an active portion and a breakdown voltage structure portion, the active portion has: a p-type base region provided in the drift layer; an n-type main region provided on the upper surface side of the base region; a p-type buried region provided in contact with the base region on the upper surface side of the drift layer; and a p-type base contact region provided in contact with the main region on the upper surface side of the buried region, the breakdown voltage structure portion has: p-type electric field relaxation regions containing SiC provided on the upper surface side of the drift layer, each of the main region and the base contact region containing SiC contains a 3C-structure in at least a part in contact with the main electrode, and the electric field relaxation regions are composed of a 4H-structure.

Abstract: A silicon carbide semiconductor device includes: drift layer provided over an active portion and a breakdown voltage structure portion, the active portion has: a p-type base region provided in the drift layer; an n-type main region provided on the upper surface side of the base region; a p-type buried region provided in contact with the base region; and a p-type base contact region provided in contact with the main region on the upper surface side of the buried region, the breakdown voltage structure portion has: p-type electric field relaxation regions provided on the upper surface side of the drift layer, each of the main region and the base contact region contains a 3C-structure in at least a part in contact with the main electrode, and the electric field relaxation regions contain a 3C-structure in an upper portion and contain a 4H-structure in a lower portion.

Abstract: A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p??-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p+-type extension and the innermost one of the p??-type regions, at a position overlapping a border between the p+-type extension and the innermost one of the p??-type regions. The FLRs are formed concurrently with p++-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p++-type contact regions. An n+-type channel stopper region is formed concurrently with n+-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n+-type source regions.

Abstract: A p-type impurity concentration profile in a depth direction of a p-type base region is adjusted by two or more stages of ion implantation to the p-type base region. The two or more stages of ion implantation are each set to have a mutually different acceleration voltage and a dose amount that is lower the higher is the acceleration voltage. The p-type impurity concentration profile is asymmetrical about a depth position of a highest impurity concentration and the impurity concentration decreases from this depth position in a direction to n+-type source regions and in a direction to an n+-type drain region. In the p-type impurity concentration profile, the impurity concentration decreases, forming a step at one or more different depth positions closer to the n+-type drain region than is the depth position of the highest impurity.

Abstract: N+-type source regions, low-concentration regions, and p++-type contact regions are each selectively provided in surface regions of a semiconductor substrate, at a front surface thereof, and are in contact with a source electrode. The n+-type source regions and the low-concentration regions are in contact with a gate insulating film at sidewalls of a trench and are adjacent to channel portions of a p-type base region, in a depth direction. The p++-type contact regions are disposed apart from the trench. In surface regions of an epitaxial layer constituting the p-type base region, portions left free of the n+-type source regions and the p++-type contact regions configure the low-concentration regions of an n?-type or a p?-type. The low-concentration regions are disposed periodically along the trench, between the trench and the p++-type contact regions. By the described structure, short-circuit withstand capability may be increased without increasing the number of processes.

Abstract: A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; first semiconductor regions of the first conductivity type; trenches; gate insulating films; gate electrodes; first high-concentration regions of the second conductivity type provided at positions facing the trenches in a depth direction; second high-concentration regions of the second conductivity type, selectively provided between the trenches and in contact with the first semiconductor regions, each having an upper surface exposed at the surface of the second semiconductor layer and a lower surface partially in contact with upper surfaces of the first high-concentration regions; a first electrode; and a second electrode. The second high-concentration regions are disposed periodically in a longitudinal direction of the trenches.

Abstract: A manufacturing method of a silicon carbide semiconductor device includes: epitaxially growing a drift layer of a first conductivity-type on a silicon carbide substrate of the first conductivity-type; forming a base region of a second conductivity-type on the drift layer; forming a main region of the first conductivity-type on the drift layer so as to be in contact with the base region; forming a gate insulating film so as to be in contact with the base region and the main region; forming a gate electrode so as to be in contact with the base region and the main region with the gate insulating film interposed; and forming a lifetime killer region at a depth covering a bottom surface of the drift layer by irradiating the top surface side of the drift layer with a lifetime killer after epitaxially growing the drift layer and before forming the gate insulating film.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, first base regions of a second conductivity type, second base regions of the second conductivity type, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, and trenches. Between adjacent first base regions, at least two of the trenches, at least two of the gate electrodes, and at least two of the second base regions are disposed, the second base regions disposed between the adjacent first base regions being disposed separate from one another and separate from the first base regions, in a direction in which the trenches are arranged.

Abstract: In a silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of a source electrode is applied to the gate electrode is limited to less than 2×10?11 A and the gate leak current is limited to less than 3.7×10?6 A/m2.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern.

Abstract: In an edge termination region, p-type regions and p?-type regions configuring a spatial modulation JTE structure are selectively provided at depth positions apart from a front surface of a semiconductor substrate. Respective bottoms of the p-type regions and the p?-type regions are at depth positions deeper from the front surface of the semiconductor substrate than is a bottom of a p-type peripheral region of a peripheral portion of an active region. An outer-side corner of the bottom of the p-type peripheral region is surrounded by an innermost one of the p-type regions and is free from contact with an n?-type drift region of the edge termination region.

Abstract: A method of manufacturing an insulated gate semiconductor device includes simultaneously forming a gate trench and a contact trench that respectively penetrate form a top of the electrode contact region through a main electrode contact region and a injection control region in a depth direction and respectively reach a charge transport region, the contact trench being disposed at a position laterally separated from the gate trench in a plan view; and embedding a gate electrode inside the gate trench with a gate insulating film interposed therebetween, thereby forming an insulated gate structure, and simultaneously embedding an injection suppression region inside the contact trench, the gate electrode and the injection suppression region being both made of a second semiconductor material having a narrower bandgap than a bandgap of the first semiconductor material of the charge transport region.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern.

Abstract: First p+-type regions are provided directly beneath trenches, separate from a p-type base region and facing bottoms of the trenches in a depth direction. The first p+-type regions are exposed at the bottoms of the trenches and are in contact with a gate insulating film at the bottoms of the trenches. Second p+-type regions are each provided between (mesa region) adjacent trenches, separate from the first p+-type regions and the trenches. Drain-side edges of the second p+-type regions are positioned closer to a source side than are drain-side edges of the first p+-type regions. In each mesa region, an n+-type region is provided separate from the first p+-type regions and the trenches. The n+-type regions are adjacent to and face the second p+-type regions in the depth direction.

Abstract: A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, a gate insulating film, gate electrodes, first electrodes, a second electrode, and a gate pad portion configured by a gate electrode pad and a connecting portion. The second semiconductor layer includes a first region facing the connecting portion and a second region facing a corner portion of the gate electrode pad, and the first and second regions are free of the second semiconductor regions. The oxide film is provided on surfaces of the second semiconductor regions and the first and second regions, and the oxide film and the gate insulating film are made of a same material.

Abstract: A silicon carbide semiconductor device including a silicon carbide semiconductor substrate. The silicon carbide semiconductor substrate has an active region through which a main current flows, and a termination region surrounding a periphery of the active region in a top view of the silicon carbide semiconductor device. In the top view, the active region is of a rectangular shape, which has two first sides in a <11-20> direction and two second sides in a <1-100> direction. The two first sides are each of a first length, and the two second sides are each of a second length, the first length being longer than the second length.

Abstract: In an edge termination region, a FLR structure configured by FLRs having a floating potential and surrounding concentrically a periphery of an active region is provided. The FLR structure is divided into at least two FLR segments with a predetermined FLR as a boundary. An n-th interval between an adjacent two of the FLRs is wider than a first interval between a p+-type extension portion and the FLR closest to a chip center (n=2 to total number of the FLRs). The n-th interval between an adjacent two of the FLRs increases in arithmetic progression the closer the adjacent two are to a chip end, the n-th interval increasing in arithmetic progression by a corresponding one of constant increase increments respectively corresponding to the FLR segments; the closer a FLR segment is to the chip end, the wider is the constant increase increment corresponding thereto.

Abstract: A semiconductor device, including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided on the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at a surface thereof, a plurality of gate insulating films in contact with the second semiconductor layer, a plurality of gate electrodes respectively provided on the gate insulating films, a plurality of first electrodes provided on the second semiconductor layer and the first semiconductor regions, and a second electrode provided on a back surface of the semiconductor substrate.

Abstract: A semiconductor device includes an active region through which a main current passes during an ON state. In the active region, the semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, first trenches, a second trench, a polycrystalline silicon layer provided in the second trench via one of the gate insulating films, and a silicide layer selectively provided in a surface layer of the polycrystalline silicon layer. The polycrystalline silicon layer and the silicide layer are electrically connected with the gate electrodes.