Patents by Inventor Akimasa Kinoshita

Akimasa Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210074849
    Abstract: First p+-type regions are provided directly beneath trenches, separate from a p-type base region and facing bottoms of the trenches in a depth direction. The first p+-type regions are exposed at the bottoms of the trenches and are in contact with a gate insulating film at the bottoms of the trenches. Second p+-type regions are each provided between (mesa region) adjacent trenches, separate from the first p+-type regions and the trenches. Drain-side edges of the second p+-type regions are positioned closer to a source side than are drain-side edges of the first p+-type regions. In each mesa region, an n+-type region is provided separate from the first p+-type regions and the trenches. The n+-type regions are adjacent to and face the second p+-type regions in the depth direction.
    Type: Application
    Filed: August 3, 2020
    Publication date: March 11, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Akimasa Kinoshita
  • Patent number: 10937901
    Abstract: Provided are: injection control regions of a second conductivity type provided on a charge transport region of a first conductivity type; main electrode regions of the first conductivity type provided on the injection control regions; insulated gate electrode structures going through the main electrode region and the injection control regions in the depth direction; an injection suppression region going through the main electrode regions and the injection control regions in the depth direction so as to form a pn junction in a path leading to the charge transport region, the injection suppression region including a semiconductor material with a narrower bandgap than a material of the charge transport region; and a contact protection region of the second conductivity type contacting the bottom surface of the injection suppression region.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: March 2, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Akimasa Kinoshita
  • Publication number: 20210020751
    Abstract: In a silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of a source electrode is applied to the gate electrode is limited to less than 2×10?11 A and the gate leak current is limited to less than 3.7×10?6 A/m2.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Keiji OKUMURA, Akimasa KINOSHITA
  • Patent number: 10886371
    Abstract: A silicon carbide semiconductor device, including a semiconductor substrate having first and second epitaxial layers. The second epitaxial layer is formed on a first main surface of the semiconductor substrate, and includes first and second semiconductor regions, selectively provided in a surface layer of the second epitaxial layer respectively in the active region and the border region, and a third semiconductor region. The semiconductor device further includes a trench penetrating the first and third semiconductor regions to reach the first epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a first electrode electrically connected to the first and third semiconductor regions, and a second electrode provided at a second main surface of the semiconductor substrate. The second semiconductor region is separate from the first semiconductor region.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: January 5, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Tsuji, Akimasa Kinoshita
  • Patent number: 10879386
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a gate electrode provided via a gate insulating film, an interlayer insulating film, and a barrier metal. At a temperature T (K) and where a guaranteed time of no negative bias temperature instability is L (h), a surface density tTi1 of Ti contained in the barrier metal satisfies: t Ti ? ? 1 > 1 1.58 × 10 5 ? { ln ? ( L 1.74 × 10 - 8 ) + Ea 473 × k - Ea kT } where, k is Boltzmann's constant, and Ea is activation energy satisfying 1.0 (eV)<Ea<1.5 (eV).
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: December 29, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Akimasa Kinoshita
  • Patent number: 10840340
    Abstract: In a MOS silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of the source electrode is applied to the gate electrode is limited to less than 2×10?11 A. The negative voltage applied to the gate electrode is limited to ?3V or lower relative to the potential of the source electrode.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keiji Okumura, Akimasa Kinoshita
  • Publication number: 20200295129
    Abstract: A semiconductor device includes lower and upper parallel pn structures. The lower parallel pn structure is disposed at a first semiconductor layer and includes lower first columns of a first conductivity type and lower second columns of a second conductivity type, the lower first and second columns each having a stripe shape, extending in a first direction and being disposed repeatedly alternating with one another in a plane parallel to a front surface. The upper parallel pn structure is disposed at the lower parallel pn structure and includes upper first columns of the first conductivity type and upper second columns of the second conductivity type, the upper first and second columns each having a stripe shape, extending in a second direction different than the first direction and disposed repeatedly alternating with one another in a plane parallel to the front surface.
    Type: Application
    Filed: January 27, 2020
    Publication date: September 17, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Akimasa KINOSHITA
  • Patent number: 10692979
    Abstract: A method of manufacturing a semiconductor device includes providing a silicon carbide (SiC) substrate, forming a SiC layer on a front surface of the SiC substrate, selectively forming a first region in the SiC layer at a surface thereof, forming a source region and a contact region in the first region, forming a gate insulating film on the SiC layer and on a portion of the first region between the SiC layer and the source region, forming a gate electrode on the gate insulating film above the portion of the first region, forming an interlayer insulating film covering the gate electrode, forming a source electrode electrically connected to the source region and the contact region, forming a drain electrode on a back surface of the SiC substrate, forming a barrier film on and covering the interlayer insulating film, and forming a metal electrode on the source electrode and the barrier film.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 23, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Harada, Yasuyuki Hoshi, Akimasa Kinoshita, Yasuhiko Oonishi
  • Patent number: 10644145
    Abstract: A semiconductor device, including a semiconductor substrate, a semiconductor layer disposed on a surface of the semiconductor substrate, a first semiconductor region disposed in the semiconductor layer at a surface thereof, a source region and a second semiconductor region disposed in the first semiconductor region at a surface thereof, a source electrode contacting the source region and the second semiconductor region, a gate insulating film disposed on the surface of the semiconductor layer and covering a portion of the first semiconductor region between the source region and the semiconductor layer, a gate electrode disposed on a surface of the gate insulating film, a drain electrode disposed on another surface of the semiconductor substrate, and a third semiconductor region, which has an impurity concentration higher than that of the first semiconductor region, formed in the semiconductor layer at the surface thereof and being electrically connected to the source electrode.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: May 5, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Hoshi, Yuichi Harada, Akimasa Kinoshita, Yasuhiko Oonishi
  • Publication number: 20200119147
    Abstract: A trench gate MOSFET has at an n-type current spreading region between an n?-type drift region and a p-type base region, a first p+-type region facing a bottom of a trench, and a second p+-type region disposed between adjacent trenches. The first and the second p+-type regions extend parallel to a first direction in which the trench extends and are partially connected by a p+-type connecting portion and thus, disposed in a ladder shape when viewed from the front surface of a semiconductor substrate. The second p+-type region has at a portion of a surface on a drain side, a recessed portion that is recessed toward a source side. One or more recessed portions is provided between connection sites in the second p+-type region for connection with the p+-type connecting portions that are adjacent to each other in the first direction X.
    Type: Application
    Filed: August 23, 2019
    Publication date: April 16, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa KINOSHITA, Keiji Okumura
  • Patent number: 10622446
    Abstract: A semiconductor device includes in an active region in which current flows, an n+-type silicon carbide epitaxial layer of a low concentration and formed on an n+-type silicon carbide substrate; a p-type channel region constituting a channel region; a trench contacting the p-type channel region and having embedded therein an oxide film and a gate electrode; a p+-type base layer arranged beneath the trench; a third n-type CSL layer region contacting the p-type channel region; a second n-type CSL layer region having a maximum impurity concentration higher than that of the third n-type CSL layer region, the maximum impurity concentration being farther on a substrate front side than a top of the p+-type base layer arranged beneath the trench is; and a first n-type CSL layer region contacting the second n-type CSL layer region and having a maximum impurity concentration lower than that of the second n-type CSL layer region.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Akimasa Kinoshita, Shinsuke Harada
  • Patent number: 10600864
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a trench; a second semiconductor region of the second conductivity type; a third semiconductor region of the second conductivity type; and a fourth semiconductor region of the first conductivity type. The second semiconductor region is selectively provided inside the first semiconductor layer, and the third semiconductor region is selectively provided inside the first semiconductor layer and contacts a bottom surface of the trench. The fourth semiconductor region is provided perpendicularly to a lengthwise direction of the trench in a plan view and is located at a depth position that is deeper than the second semiconductor region.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Keiji Okumura
  • Publication number: 20200083338
    Abstract: A gate pad includes a first portion disposed in a gate pad region and a second portion continuous with the first portion and disposed in a gate resistance region. The gate pad has a planar shape in which the second portion protrudes from the first portion. A gate polysilicon layer provided on a front surface of a semiconductor substrate via a gate insulating film is disposed between the semiconductor substrate and an interlayer insulating film, has a surface area that is at least equal to a surface area of the gate pad, and faces the gate pad in a depth direction. The gate polysilicon layer has a planar outline similar to that of the gate pad and includes continuous first and second portions, the first portion facing the first portion of the gate pad overall, and a second portion facing the second portion of the gate pad.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 12, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Akimasa KINOSHITA
  • Publication number: 20200006494
    Abstract: A silicon carbide semiconductor device, including a semiconductor substrate having first and second epitaxial layers. The second epitaxial layer is formed on a first main surface of the semiconductor substrate, and includes first and second semiconductor regions, selectively provided in a surface layer of the second epitaxial layer respectively in the active region and the border region, and a third semiconductor region. The semiconductor device further includes a trench penetrating the first and third semiconductor regions to reach the first epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a first electrode electrically connected to the first and third semiconductor regions, and a second electrode provided at a second main surface of the semiconductor substrate. The second semiconductor region is separate from the first semiconductor region.
    Type: Application
    Filed: April 19, 2019
    Publication date: January 2, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi TSUJI, Akimasa KINOSHITA
  • Patent number: 10522676
    Abstract: A MOS gate having a trench gate structure is formed on the front surface side of a silicon carbide substrate. A gate trench of the trench gate structure goes through an n+ source region and a p-type base region and reaches an n? drift region. Between adjacent gate trenches, a first p+ region that goes through the p-type base region in the depth direction and reaches the n? drift region is formed at a position separated from the gate trenches. The first p+ region is formed directly beneath a p++ contact region. The width of the first p+ region is less than the width w1 of the gate trench. A second p+ region is formed at the bottom of the gate trench. The first and second p+ regions are silicon carbide epitaxial layers.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Akimasa Kinoshita
  • Publication number: 20190348502
    Abstract: A method of manufacturing a semiconductor device includes providing a silicon carbide (SiC) substrate, forming a SiC layer on a front surface of the SiC substrate, selectively forming a first region in the SiC layer at a surface thereof, forming a source region and a contact region in the first region, forming a gate insulating film on the SiC layer and on a portion of the first region between the SiC layer and the source region, forming a gate electrode on the gate insulating film above the portion of the first region, forming an interlayer insulating film covering the gate electrode, forming a source electrode electrically connected to the source region and the contact region, forming a drain electrode on a back surface of the SiC substrate, forming a barrier film on and covering the interlayer insulating film, and forming a metal electrode on the source electrode and the barrier film.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi HARADA, Yasuyuki HOSHI, Akimasa KINOSHITA, Yasuhiko OONISHI
  • Publication number: 20190288073
    Abstract: In a MOS silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of the source electrode is applied to the gate electrode is limited to less than 2×10?11 A. The negative voltage applied to the gate electrode is limited to ?3V or lower relative to the potential of the source electrode.
    Type: Application
    Filed: January 23, 2019
    Publication date: September 19, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Keiji OKUMURA, Akimasa KINOSHITA
  • Publication number: 20190288104
    Abstract: Provided are: injection control regions of a second conductivity type provided on a charge transport region of a first conductivity type; main electrode regions of the first conductivity type provided on the injection control regions; insulated gate electrode structures going through the main electrode region and the injection control regions in the depth direction; an injection suppression region going through the main electrode regions and the injection control regions in the depth direction so as to form a pn junction in a path leading to the charge transport region, the injection suppression region including a semiconductor material with a narrower bandgap than a material of the charge transport region; and a contact protection region of the second conductivity type contacting the bottom surface of the injection suppression region.
    Type: Application
    Filed: February 6, 2019
    Publication date: September 19, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Akimasa KINOSHITA
  • Patent number: 10418477
    Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Akimasa Kinoshita, Shinsuke Harada, Yasunori Tanaka
  • Patent number: 10403749
    Abstract: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 3, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Shinsuke Harada, Yasunori Tanaka