Abstract: A method of manufacturing a semiconductor device includes providing a silicon carbide (SiC) substrate, forming a SiC layer on a front surface of the SiC substrate, selectively forming a first region in the SiC layer at a surface thereof, forming a source region and a contact region in the first region, forming a gate insulating film on the SiC layer and on a portion of the first region between the SiC layer and the source region, forming a gate electrode on the gate insulating film above the portion of the first region, forming an interlayer insulating film covering the gate electrode, forming a source electrode electrically connected to the source region and the contact region, forming a drain electrode on a back surface of the SiC substrate, forming a barrier film on and covering the interlayer insulating film, and forming a metal electrode on the source electrode and the barrier film.

Abstract: Provided are: injection control regions of a second conductivity type provided on a charge transport region of a first conductivity type; main electrode regions of the first conductivity type provided on the injection control regions; insulated gate electrode structures going through the main electrode region and the injection control regions in the depth direction; an injection suppression region going through the main electrode regions and the injection control regions in the depth direction so as to form a pn junction in a path leading to the charge transport region, the injection suppression region including a semiconductor material with a narrower bandgap than a material of the charge transport region; and a contact protection region of the second conductivity type contacting the bottom surface of the injection suppression region.

Abstract: In a MOS silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of the source electrode is applied to the gate electrode is limited to less than 2×10?11 A. The negative voltage applied to the gate electrode is limited to ?3V or lower relative to the potential of the source electrode.

Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.

Abstract: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.

Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

Abstract: A semiconductor device having a silicon carbide (SiC) substrate, a SiC layer formed on a front surface of the SiC substrate, a first region selectively formed in the SiC layer at a surface thereof, a source region and a contact region formed in the first region, a gate insulating film disposed on the SiC layer and on a portion of the first region between the SiC layer and the source region, a gate electrode disposed on the gate insulating film above the portion of the first region, an interlayer insulating film covering the gate electrode, a source electrode electrically connected to the source region and the contact region, a drain electrode formed on a back surface of the SiC substrate, a first barrier film formed on, and covering, the interlayer insulating film, and a metal electrode formed on the source electrode and the first barrier film.

Abstract: A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor layer of the first conductivity type provided on a front surface of the wide-bandgap semiconductor substrate of the first conductivity type, a base region of a second conductivity type selectively provided in a surface layer of the wide-bandgap semiconductor layer of the first conductivity type, and a trench having a striped planar pattern. The base regions are cyclically provided in a direction parallel to the trench. At the lower portion of the trench, a portion of the base region extends in a direction parallel to the trench and the base regions are connected to each other.

Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a trench; a second semiconductor region of the second conductivity type; a third semiconductor region of the second conductivity type; and a fourth semiconductor region of the first conductivity type. The second semiconductor region is selectively provided inside the first semiconductor layer, and the third semiconductor region is selectively provided inside the first semiconductor layer and contacts a bottom surface of the trench. The fourth semiconductor region is provided perpendicularly to a lengthwise direction of the trench in a plan view and is located at a depth position that is deeper than the second semiconductor region.

Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a gate electrode provided via a gate insulating film, an interlayer insulating film, and a barrier metal. At a temperature T (K) and where a guaranteed time of no negative bias temperature instability is L (h), a surface density tTi1 of Ti contained in the barrier metal satisfies: t Ti ? ? 1 > 1 1.58 × 10 5 ? { ln ? ( L 1.74 × 10 - 8 ) + Ea 473 × k - Ea kT } where, k is Boltzmann's constant, and Ea is activation energy satisfying 1.0 (eV)<Ea<1.5 (eV).

Abstract: A semiconductor device includes a silicon carbide semiconductor substrate, a first silicon carbide layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The third semiconductor region is thicker than the second semiconductor region and a width of a side of the third semiconductor region facing the first semiconductor region is narrower than a width of a side thereof facing the source electrode.

Abstract: A MOS gate is provided on a front surface side of a silicon carbide substrate. The silicon carbide substrate includes silicon carbide layers sequentially formed on an n+-type starting substrate by epitaxial growth. Of the silicon carbide layers, a p+-type silicon carbide layer is a p+-type high-concentration base region and is separated into plural regions by a trench. A p-type silicon carbide layer among the silicon carbide layers covers the p+-type silicon carbide layer and is embedded in the trench. A p-type silicon carbide layer among the silicon carbide layers is a p-type base region. From a substrate front surface, a gate trench penetrates the p-type base region in the trench and the n+-type source region to reach an n?-type drift region. Between the p+-type high-concentration base region and a gate insulating film at a sidewall of the gate trench, the p-type base region is embedded in the trench.

Abstract: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.

Abstract: An insulated-gate semiconductor device includes: an n+-type current spreading layer disposed on an n?-type drift layer; a p-type base region disposed on the current spreading layer; a n+-type main-electrode region arranged in an upper portion of the base region; an insulated-gate electrode structure provided in a trench; and a p+-type gate-bottom protection-region being in contact with a bottom of the trench, including a plurality of openings through which a part of the current spreading layer penetrates, being selectively buried in the current spreading layer, wherein positions of the openings cut on both sides of a central line of the trench are shifted from each other about the central line in a longitudinal direction of the trench in a planar pattern.

Abstract: A MOS gate having a trench gate structure is formed on the front surface side of a silicon carbide substrate. A gate trench of the trench gate structure goes through an n+ source region and a p-type base region and reaches an n? drift region. Between adjacent gate trenches, a first p+ region that goes through the p-type base region in the depth direction and reaches the n? drift region is formed at a position separated from the gate trenches. The first p+ region is formed directly beneath a p++ contact region. The width of the first p+ region is less than the width w1 of the gate trench. A second p+ region is formed at the bottom of the gate trench. The first and second p+ regions are silicon carbide epitaxial layers.

Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

Abstract: A MOS gate having a trench gate structure is formed on the front surface side of a silicon carbide substrate. A gate trench of the trench gate structure goes through an n+ source region and a p-type base region and reaches an n? drift region. Between adjacent gate trenches, a first p+ region that goes through the p-type base region in the depth direction and reaches the n? drift region is formed at a position separated from the gate trenches. The first p+ region is formed directly beneath a p++ contact region. The width of the first p+ region is less than the width w1 of the gate trench. A second p+ region is formed at the bottom of the gate trench. The first and second p+ regions are silicon carbide epitaxial layers.

Abstract: A semiconductor device includes an active region provided in an n+-type silicon carbide substrate and through which main current flows, a termination region that surrounds a periphery of the active region, and a p-type silicon carbide layer provided on a front surface of the n+-type silicon carbide substrate and extending into the termination region. A region of the p-type silicon carbide layer extending into the termination region includes one or more step portions that progressively reduce a thickness of the p-type silicon carbide layer as the p-type silicon carbide layer becomes farther outward from the active region.

Abstract: A gate trench of a MOS gate formed in the front surface of a silicon carbide substrate includes a first portion that includes the bottom surface of the gate trench, a second portion that is connected to the substrate front surface side of the first portion, and a third portion that is connected to the substrate front surface side of the second portion. In the third portion of the gate trench, an n+ source region is exposed along the sidewalls. The width of the third portion of the gate trench is greater than the widths of the first and second portions and of the gate trench. Upper corners of the gate trench smoothly connect the sidewalls to the substrate front surface. The thickness of a gate insulating film smoothly connected along the bottom surface and sidewalls of the gate trench is substantially uniform over the entire inner wall surface of the gate trench.