Abstract: An active region through which current flows in a semiconductor device includes an n?-type silicon carbide epitaxial layer formed on a front surface of an n+-type silicon carbide semiconductor substrate; a p-type layer becoming a channel region; a trench formed so as to be in contact with a p-type layer and having an oxide film and a gate electrode embedded therein; a p+-type layer arranged beneath the trench and between trenches; an n?-type layer in contact with the p-type layer, a p+-type layer, and the trench, and arranged in contact with a p+-type layer or on a surface side of the semiconductor substrate; an n-type layer in contact with the n?-type silicon carbide epitaxial layer and the p+-type layer, and having an impurity concentration higher than that of the n?-type layer and that of the n?-type silicon carbide epitaxial layer.

Abstract: A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p+-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p+-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p?-type region constituting an edge termination structure provided in the flat portion.

Abstract: Process (A) of preparing a silicon carbide substrate of a first conductivity type; process (B) of forming an epitaxial layer of the first conductivity type on one principal surface of the silicon carbide substrate; process (C) of forming on another principal surface of the silicon carbide substrate, a first metal layer; process (D) of heat treating the silicon carbide substrate after the process (C) to form an ohmic junction between the first metal layer and the other principal surface of the silicon carbide substrate, and a layer of a substance (10) highly cohesive with another metal on the first metal layer; and a process (E) of removing impurities and cleaning a surface of the first metal layer (8) on the other principal surface of the silicon carbide substrate (D), are performed. The heat treatment at process (D) is executed at a temperature of 1,100 degrees C. or more.

Abstract: A semiconductor device includes: an n+-type drain region made of a wide-bandgap semiconductor material; an n-type epitaxial layer provided on the top surface of the drain region; an n-type first semiconductor region provided at an upper portion of the epitaxial layer and having a higher impurity concentration than the epitaxial layer; an n-type second semiconductor region provided on the first semiconductor region and having a higher impurity concentration than the first semiconductor region; p-type base regions surrounding to include an upper portion in the middle of the second semiconductor region; n-type source regions provided at upper portions of the base regions to form a channel; and a gate electrode which controls a surface potentials of the channels.

Abstract: A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p+-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p+-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p?-type region constituting an edge termination structure provided in the flat portion.

Abstract: In a fabrication method of a silicon carbide semiconductor element including a drift layer playing a role of retaining a high withstand voltage on a front side of a semiconductor substrate of silicon carbide and including an ohmic electrode on a backside, dicing is added to form at least one dicing line in an element active region on a surface of the semiconductor substrate on a side opposite of the drift layer before forming the ohmic electrode on the backside of the semiconductor substrate. Thus, a silicon carbide semiconductor element and fabrication method thereof is provided such that even if the semiconductor substrate is made thinner to reduce the on-resistance, the strength of the substrate can be maintained and cracking of the wafer during wafer processing can be reduced.

Abstract: A semiconductor device includes an n+ type silicon carbide substrate, and in the substrate an active region where primary current flows and an edge termination area surrounding the active region. The semiconductor device has a first p-type region and a second p-type region in the edge termination area, and the first p-type region includes therein a plurality of third p-type regions, and the second p-type region includes therein a plurality of fourth p-type regions. The widths between the respective plurality of third p-type regions and the widths between the respective plurality of fourth p-type regions become greater further away from the active region.

Abstract: A semiconductor device includes an n+ type silicon carbide substrate, and in the substrate an active region where primary current flows and an edge termination area surrounding the active region. The semiconductor device has a first p-type region and a second p-type region in the edge termination area, and the first p-type region includes therein a plurality of third p-type regions, and the second p-type region includes therein a plurality of fourth p-type regions. The widths between the respective plurality of third p-type regions and the widths between the respective plurality of fourth p-type regions become greater further away from the active region.

Abstract: A semiconductor device having a silicon carbide (SiC) substrate, a SiC layer formed on a front surface of the SiC substrate, a first region selectively formed in the SiC layer at a surface thereof, a source region and a contact region formed in the first region, a gate insulating film disposed on the SiC layer and on a portion of the first region between the SiC layer and the source region, a gate electrode disposed on the gate insulating film above the portion of the first region, an interlayer insulating film covering the gate electrode, a source electrode electrically connected to the source region and the contact region, a drain electrode formed on a back surface of the SiC substrate, a first barrier film formed on, and covering, the interlayer insulating film, and a metal electrode formed on the source electrode and the first barrier film.

Abstract: A semiconductor device, including a semiconductor substrate, a semiconductor layer disposed on a surface of the semiconductor substrate, a first semiconductor region disposed in the semiconductor layer at a surface thereof, a source region and a second semiconductor region disposed in the first semiconductor region at a surface thereof, a source electrode contacting the source region and the second semiconductor region, a gate insulating film disposed on the surface of the semiconductor layer and covering a portion of the first semiconductor region between the source region and the semiconductor layer, a gate electrode disposed on a surface of the gate insulating film, a drain electrode disposed on another surface of the semiconductor substrate, and a third semiconductor region, which has an impurity concentration higher than that of the first semiconductor region, formed in the semiconductor layer at the surface thereof and being electrically connected to the source electrode.

Abstract: A semiconductor device includes an N-type silicon carbide layer, a P-type region, an N-type source region, a P-type contact region, a gate insulating film, a gate electrode, and a source electrode on the front surface side of an N-type silicon carbide substrate. A drain electrode is located on the back surface of the N-type silicon carbide substrate. A life time killer introduction region is located along an entire interface of the N-type silicon carbide layer and the bottom face of the P-type region. The life time killer is introduced by implanting helium or protons from the back surface side of the N-type silicon carbide substrate after forming a surface structure of an element on the front surface side of the N-type silicon carbide substrate and before forming the drain electrode.

Abstract: A semiconductor device includes an n+-type source region having an impurity concentration higher than that of an n-type source region, formed in a surface layer of a p-type SiC layer and a p-type base region, farther on an outer side than the n-type source region, and contacting the n-type source region; an n-type region and an n+-type region having an impurity concentration higher than that of the n?-type SiC layer, formed in a portion of the n?-type SiC layer between p-type base regions and p-type SiC layers; and a second n-type region under the p-type base region and of a size smaller than that of the p-type base region, whereby low on-resistance and precision of the threshold voltage Vth are enhanced, increasing quality and enabling improved resistance to dielectric breakdown of the gate insulating film and resistance to breakdown.

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a plurality of base regions of a second conductivity type formed on a first principal surface of the semiconductor substrate via a semiconductor layer of the first conductivity type, and a plurality of source regions of the first conductivity type formed in the base regions. Each base region, in a top-down view from an angle perpendicular to the first principle surface, is of a polygonal shape. Each adjacent two of the base regions in the top-down view have two sides, one from each of the two base regions, that face each other across a portion of the semiconductor layer, the source region being formed at only one of the two sides.

Abstract: A semiconductor device includes an N-type silicon carbide substrate, an N-type silicon carbide layer formed on the N-type silicon carbide substrate, a P-type region selectively formed in a surface layer of the N-type silicon carbide layer, an N-type source region formed in the P-type region, a P contact region formed in the P-type region, a gate insulating film formed on a portion of a region from the N-type source region, through the P-type region, to the N-type silicon carbide layer, a gate electrode formed on the gate insulating film, an interlayer insulating film covering the gate electrode, and a first source electrode electrically connected to a surface of the P contact region and the N-type source region. An end of the interlayer insulating film covering the gate electrode has a slope of a predetermined angle.

Abstract: A semiconductor device includes on an n-type semiconductor substrate of silicon carbide, an n-type semiconductor layer, a p-type base region, an n-type source region, a p-type contact region, a gate insulating film, a gate electrode, and a source electrode. The semiconductor device has a drain electrode on a back surface of the semiconductor substrate. On a surface of the gate electrode, an interlayer insulating film is disposed. The interlayer insulating film has plural layers among which, one layer is formed by a silicon nitride film. With such a structure, degradation of semiconductor device properties are suppressed. Further, increases in the number of processes at the time of manufacturing are suppressed.

Abstract: A semiconductor device of an embodiment includes a p+-type region selectively disposed in a surface of an n-type silicon carbide epitaxial layer disposed on an n+-type silicon carbide substrate, an element structure that includes a source electrode and a p+-type region that form a metal-semiconductor junction on the n-type silicon carbide epitaxial layer, a p?-type region and another p?-type region that surround the periphery of the element structure, and an n+-type channel stopper region that surrounds the periphery of the p?-type regions so that the n-type silicon carbide epitaxial layer is therebetween. The n+-type channel stopper region has a second n+-type channel stopper region whose impurity concentration is high, and a first n+-type channel stopper region that encompasses the second n+-type channel stopper region and whose impurity concentration is lower than that of the second n+-type channel stopper region.

Abstract: A wide bandgap semiconductor device includes a first conductive type high-concentration wide bandgap semiconductor substrate, a first conductive type low-concentration wide bandgap semiconductor deposited film which is formed on the semiconductor substrate, a metal film which is formed on the semiconductor deposited film so that a Schottoky interface region is formed between the metal film and the semiconductor deposited film, and a second conductive type region which is formed in a region of the semiconductor deposited film corresponding to a peripheral portion of the metal film, wherein the Schottoky interface region in the semiconductor deposited film is surrounded by the second conductive type region so that periodic island regions are formed in the Schottoky interface region.

Abstract: P+ type regions and a p-type region are selectively disposed in a surface layer of a silicon carbide substrate base. The P+ type region is disposed in a breakdown voltage structure portion surrounding an active region. The P+ type region is disposed in the active region to make up a JBS structure. The p-type region surrounds the P+ type region to make up a junction termination (JTE) structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode overhangs an interlayer insulation film covering a portion of the P+ type region and the p-type region and this overhanging portion acts as a field plate. This enables the provision of a semiconductor device configured by using a wide band gap semiconductor capable of maintaining a high breakdown voltage with high reliability, and a method of fabricating thereof.

Abstract: An ohmic electrode (6) of a silicon carbide semiconductor apparatus is fabricated by forming an ohmic metal film on a silicon carbide substrate (1) by sputtering a target including a mixture or an alloy having therein nickel, and a metal(s) reducing the magnetic permeability of nickel and producing a carbide, where compositional ratios of the mixture or alloy are adjusted to predetermined compositional ratios, and by executing heat treatment for the ohmic metal film to calcinate the ohmic metal film. Thus, the ohmic electrode (6) that is for the silicon carbide semiconductor apparatus and capable of improving the use efficiency of the target can be manufactured, whose film thickness is even and that does not peel off.

Abstract: A surface of a silicon carbide substrate on which a graphite layer is formed is covered with a metal layer which can form carbide. Then, the silicon carbide substrate is annealed to cause reaction between a metal in the metal layer which can form carbide and carbon in the graphite layer so as to change the graphite layer between the metal layer which can form carbide and the silicon carbide substrate to a metal carbide layer. Thus, the graphite layer is removed. The adhesion between the metal layer which can form carbide and the silicon carbide substrate can be improved so that separation of the metal layer which can form carbide can be suppressed. Graphite deposits can be suppressed due to the removal of the graphite layer so that separation of a wiring metal film formed on a surface of the metal layer which can form carbide can be suppressed.