Patents by Inventor Akio Kaneko

Akio Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210088902
    Abstract: Provided is a photosensitive composition including a pigment, a compound which is represented by Formula (1) (A1-L1-Z1) and has 3000 L·mol?1·cm?1 or less of a maximum value of a molar light absorption coefficient in a wavelength range of 400 to 700 nm, a polymerizable compound, and an oxime-based photopolymerization initiator. In Formula (1), A1 represents a group including an aromatic ring, L1 represents a single bond or a divalent linking group, and Z1 represents a group represented by Formula (Z1).
    Type: Application
    Filed: December 3, 2020
    Publication date: March 25, 2021
    Applicant: FUJIFILM Corporation
    Inventors: Yasuhiro SAWAMURA, Masaomi Makino, Akio Mizuno, Yushi Kaneko, Hiroaki Idei
  • Publication number: 20210088842
    Abstract: According to one embodiment, an electronic apparatus includes a camera, a liquid crystal panel including a display portion overlaid on the camera, a light guide having a first side surface and a main surface opposed to the liquid crystal panel and a first through hole, and a light source opposed to the first side surface. The camera is provided in the first through hole.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 25, 2021
    Applicant: Japan Display Inc.
    Inventors: Akio TAKIMOTO, Toshiki KANEKO, Takuo KAITOH, Kazuhiro NISHIYAMA, Hiroyuki KIMURA
  • Publication number: 20210082957
    Abstract: Provided is a storage device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating film provided between the semiconductor layer and the gate electrode layer, the gate insulating film having a first region disposed between the gate electrode layer and the semiconductor layer and a second region disposed between the two first regions adjacent to each other in the first direction, the gate insulating film containing a hafnium oxide, in which a first thickness of the first region in the second direction from the semiconductor layer toward the gate electrode layer is smaller than a second thickness of the second region in the second direction.
    Type: Application
    Filed: June 16, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventors: Keiko SAKUMA, Akio Kaneko, Hidenori Miyagawa, Yuuichi Kamimuta
  • Patent number: 10923496
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Kenji Sugiura, Akio Nishida, Ryosuke Kaneko, Michiaki Sano
  • Patent number: 10890763
    Abstract: Provided is an information display apparatus that significantly improves light resistance with respect to sunlight. The information display apparatus, which displays video-image information on a projection surface by a virtual image, includes in a housing partly having an opening: a video-image-light generator that generates video-image light for displaying the video-image information; a video-image-light processor that performs a predetermined optical processing to a video image generated by the video-image-light generator; and a projector that projects, onto the projection surface through the opening of the housing, the video-image light optically processed by the video-image-light processor so that a viewer is capable of virtually recognizing the video-image information as a virtual image in front of the projection surface, wherein a light path in the housing is provided with a suppressor selectively suppressing a P-polarizing component of light in a visible light region.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 12, 2021
    Assignee: MAXELL, LTD.
    Inventors: Koji Hirata, Masahiko Yatsu, Toshinori Sugiyama, Akio Misawa, Shigeki Hoshino, Kazuomi Kaneko, Tatsuya Nakazawa, Takumi Nakada, Yuki Nagano, Tomoki Yamamoto
  • Publication number: 20200215647
    Abstract: A laser processing apparatus and a laser processing method for improving the processing speed and forming uniform and highly accurate through holes when processing for forming fine through holes in a matrix in a long thin plate, and a thin plate having through holes in a matrix formed by such laser processing. A laser processing apparatus includes a cylindrical body having an opening on a circumferential surface around which a thin plate to be processed is wound obliquely, a thin plate transfer for transferring a thin plate wound around the cylindrical body in the longitudinal direction of the thin plate, a motor having a rotation axis arranged coaxially with a central axis of the cylindrical body, a reflecting member fixed to a rotating shaft of the motor, a laser light emitting means for emitting pulsed light. The apparatus continuously opens through holes in the thin plate.
    Type: Application
    Filed: August 29, 2018
    Publication date: July 9, 2020
    Applicant: WIRED CO., LTD.
    Inventors: Akio YAMAKAWA, Naohiko SOMA, Mitsuyuki KANEKO
  • Publication number: 20200219895
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 9, 2020
    Inventors: Mitsuteru MUSHIGA, Kenji SUGIURA, Akio NISHIDA, Ryosuke KANEKO, Michiaki SANO
  • Patent number: 10651185
    Abstract: A semiconductor device includes a first electrode layer and a second electrode layer formed thereon to be spaced from the first electrode layer, a columnar portion penetrating the first and second electrode layers in a first direction and including a semiconductor layer, a first insulating film between the first and second electrode layers and the semiconductor layer and in contact with the first electrode layer, a charge storage layer between the second electrode layer and the first insulating film, and an insulating film between the second electrode layer and the charge storage layer. The semiconductor layer includes a first portion facing the second electrode layer in a second direction intersecting with the first direction and a second portion in contact with the first portion in the first direction. A concentration of a impurity contained in the second portion is higher than that of the impurity contained in the first portion.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akio Kaneko
  • Publication number: 20200064640
    Abstract: The head-up display apparatus includes: a vehicle information acquisition unit configured to acquire various kinds of vehicle information which can be detected by a vehicle; a controller configured to control display of a video image based on the vehicle information; a video image display configured to form the video image based on an instruction from the controller; a mirror configured to reflect the video image formed by the video image display to project onto the windshield; a mirror driver configured to change an angle of the mirror based on an instruction from the controller; and a display distance adjusting mechanism configured to adjust a display distance of the virtual image with respect to the driver, and the controller adjusts the angle of the mirror via the mirror driver based on the vehicle information such that the virtual image can be displayed with respect to the driver overlapped with the scenery.
    Type: Application
    Filed: October 20, 2016
    Publication date: February 27, 2020
    Inventors: Yuki NAGANO, Kazuomi KANEKO, Maki HANADA, Akio MISAWA, Kazuyuki TAKIZAWA
  • Publication number: 20190346676
    Abstract: Provided is an information display apparatus that significantly improves light resistance with respect to sunlight. The information display apparatus, which displays video-image information on a projection surface by a virtual image, includes in a housing partly having an opening: a video-image-light generator that generates video-image light for displaying the video-image information; a video-image-light processor that performs a predetermined optical processing to a video image generated by the video-image-light generator; and a projector that projects, onto the projection surface through the opening of the housing, the video-image light optically processed by the video-image-light processor so that a viewer is capable of virtually recognizing the video-image information as a virtual image in front of the projection surface, wherein a light path in the housing is provided with a suppressor selectively suppressing a P-polarizing component of light in a visible light region.
    Type: Application
    Filed: November 13, 2017
    Publication date: November 14, 2019
    Inventors: Koji HIRATA, Masahiko YATSU, Toshinori SUGIYAMA, Akio MISAWA, Shigeki HOSHINO, Kazuomi KANEKO, Tatsuya NAKAZAWA, Takumi NAKADA, Yuki NAGANO, Tomoki YAMAMOTO
  • Patent number: 10312257
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. A metal layer is provided in contact with at least one of the first and second semiconductor layers. The stacked body, semiconductor layers, insulating layer and metal layer are exposed to an annealing temperature sufficient to cause migration of metal in the metal layer into one of the first and second semiconductor layers.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Akio Kaneko
  • Patent number: 10299352
    Abstract: A light source control system includes a plurality of light sources, and a plurality of light source control devices. The light source control devices include a plurality of main light source control devices that transmits command signals to the other light source control devices. Each main light source control device includes a collision determination circuit that determines whether data of the command signal transmitted through a bus has collided with other data, and a restoration circuit that executes a restoration operation in the case of a collision. The collision determination circuit includes an edge detection circuit that detects change timing of a signal representing the data of the command signal, an area setting circuit that sets a collision determination area in accordance with the detected change timing detected, and a collision detection circuit that detects the presence or absence of a collision in the set collision determination area.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 21, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Ienaga, Satoshi Kaneko, Kazumi Ishii, Akio Fujii, Takahisa Gunji
  • Publication number: 20180277554
    Abstract: A semiconductor device includes a first electrode layer and a second electrode layer formed thereon to be spaced from the first electrode layer, a columnar portion penetrating the first and second electrode layers in a first direction and including a semiconductor layer, a first insulating film between the first and second electrode layers and the semiconductor layer and in contact with the first electrode layer, a charge storage layer between the second electrode layer and the first insulating film, and an insulating film between the second electrode layer and the charge storage layer. The semiconductor layer includes a first portion facing the second electrode layer in a second direction intersecting with the first direction and a second portion in contact with the first portion in the first direction. A concentration of a impurity contained in the second portion is higher than that of the impurity contained in the first portion.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Akio KANEKO
  • Publication number: 20180190669
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. A metal layer is provided in contact with at least one of the first and second semiconductor layers. The stacked body, semiconductor layers, insulating layer and metal layer are exposed to an annealing temperature sufficient to cause migration of metal in the metal layer into one of the first and second semiconductor layers.
    Type: Application
    Filed: March 1, 2018
    Publication date: July 5, 2018
    Inventor: Akio KANEKO
  • Patent number: 9929178
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. A metal layer is provided in contact with at least one of the first and second semiconductor layers. The stacked body, semiconductor layers, insulating layer and metal layer are exposed to an annealing temperature sufficient to cause migration of metal in the metal layer into one of the first and second semiconductor layers.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akio Kaneko
  • Publication number: 20180076213
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. A metal layer is provided in contact with at least one of the first and second semiconductor layers. The stacked body, semiconductor layers, insulating layer and metal layer are exposed to an annealing temperature sufficient to cause migration of metal in the metal layer into one of the first and second semiconductor layers.
    Type: Application
    Filed: February 1, 2017
    Publication date: March 15, 2018
    Inventor: Akio KANEKO
  • Publication number: 20170373082
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.
    Type: Application
    Filed: August 22, 2017
    Publication date: December 28, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Katsuyuki SEKINE, Tatsuya KATO, Fumitaka ARAI, Toshiyuki IWAMOTO, Yuta WATANABE, Wataru SAKAMOTO, Hiroshi ITOKAWA, Akio KANEKO
  • Publication number: 20170069388
    Abstract: A nonvolatile memory device includes a conductive layer, a semiconductor layer extending in a first direction on the conductive layer, a first insulating layer provided between the conductive layer and the semiconductor layer, a word line extending in a second direction on the semiconductor layer, the second direction intersecting the first direction, a charge storage layer provided between the semiconductor layer and the word line, and a circuit electrically connected to the conductive layer. The circuit applies an electric potential to the conductive layer when programming data, the electric potential of the conductive layer having the same polarity as an electric potential of the word line.
    Type: Application
    Filed: March 11, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Fumitaka ARAI, Akio KANEKO
  • Publication number: 20160071863
    Abstract: A method of manufacturing a semiconductor storage apparatus according to an embodiment includes forming an array of a plurality of memory cells. The method includes forming an interlayer insulating film that covers the memory cells. The method includes forming a first nitride film that covers an upper part of the interlayer insulating film. The method includes ion-implanting a first impurity into the first nitride film.
    Type: Application
    Filed: March 4, 2015
    Publication date: March 10, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akio KANEKO, Wataru SAKAMOTO, Takeshi MURATA
  • Patent number: 9007846
    Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a memory cell and a control unit. The memory cell has a gate electrode including a control gate and a charge storage region on a semiconductor substrate and has a channel region under the gate electrode in the semiconductor substrate. The control unit, during an erase operation where electric charges written in the charge storage region are extracted to the channel region, periodically varies a voltage which is to be applied between the control gate and the channel region.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Kaneko, Wataru Sakamoto