Patents by Inventor Akio Kaneko
Akio Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250081436Abstract: According to one embodiment, a semiconductor device includes a first electrode with a first electrode portion and a second electrode portion on the first electrode portion. An oxide semiconductor layer is on the second electrode portion. A gate electrode layer surrounds part of an outer side wall of the oxide semiconductor layer. A gate insulating layer surrounds the outer side wall of the oxide semiconductor layer such that the gate insulating layer is between the oxide semiconductor layer and the gate electrode layer. A distance between the second electrode portion and the gate electrode layer is less than a distance between the first electrode portion and the gate electrode layer.Type: ApplicationFiled: September 3, 2024Publication date: March 6, 2025Inventors: Kotaro NODA, Akio KANEKO, Masayuki MURASE, Akifumi GAWASE, Kazuhiro KATONO
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Patent number: 11437403Abstract: Provided is a storage device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating film provided between the semiconductor layer and the gate electrode layer, the gate insulating film having a first region disposed between the gate electrode layer and the semiconductor layer and a second region disposed between the two first regions adjacent to each other in the first direction, the gate insulating film containing a hafnium oxide, in which a first thickness of the first region in the second direction from the semiconductor layer toward the gate electrode layer is smaller than a second thickness of the second region in the second direction.Type: GrantFiled: June 16, 2020Date of Patent: September 6, 2022Assignee: Kioxia CorporationInventors: Keiko Sakuma, Akio Kaneko, Hidenori Miyagawa, Yuuichi Kamimuta
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Patent number: 11183507Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.Type: GrantFiled: August 22, 2017Date of Patent: November 23, 2021Assignee: Toshiba Memory CorporationInventors: Katsuyuki Sekine, Tatsuya Kato, Fumitaka Arai, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto, Hiroshi Itokawa, Akio Kaneko
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Publication number: 20210082957Abstract: Provided is a storage device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating film provided between the semiconductor layer and the gate electrode layer, the gate insulating film having a first region disposed between the gate electrode layer and the semiconductor layer and a second region disposed between the two first regions adjacent to each other in the first direction, the gate insulating film containing a hafnium oxide, in which a first thickness of the first region in the second direction from the semiconductor layer toward the gate electrode layer is smaller than a second thickness of the second region in the second direction.Type: ApplicationFiled: June 16, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Keiko SAKUMA, Akio Kaneko, Hidenori Miyagawa, Yuuichi Kamimuta
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Patent number: 10651185Abstract: A semiconductor device includes a first electrode layer and a second electrode layer formed thereon to be spaced from the first electrode layer, a columnar portion penetrating the first and second electrode layers in a first direction and including a semiconductor layer, a first insulating film between the first and second electrode layers and the semiconductor layer and in contact with the first electrode layer, a charge storage layer between the second electrode layer and the first insulating film, and an insulating film between the second electrode layer and the charge storage layer. The semiconductor layer includes a first portion facing the second electrode layer in a second direction intersecting with the first direction and a second portion in contact with the first portion in the first direction. A concentration of a impurity contained in the second portion is higher than that of the impurity contained in the first portion.Type: GrantFiled: September 1, 2017Date of Patent: May 12, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Akio Kaneko
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Patent number: 10312257Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. A metal layer is provided in contact with at least one of the first and second semiconductor layers. The stacked body, semiconductor layers, insulating layer and metal layer are exposed to an annealing temperature sufficient to cause migration of metal in the metal layer into one of the first and second semiconductor layers.Type: GrantFiled: March 1, 2018Date of Patent: June 4, 2019Assignee: Toshiba Memory CorporationInventor: Akio Kaneko
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Publication number: 20180277554Abstract: A semiconductor device includes a first electrode layer and a second electrode layer formed thereon to be spaced from the first electrode layer, a columnar portion penetrating the first and second electrode layers in a first direction and including a semiconductor layer, a first insulating film between the first and second electrode layers and the semiconductor layer and in contact with the first electrode layer, a charge storage layer between the second electrode layer and the first insulating film, and an insulating film between the second electrode layer and the charge storage layer. The semiconductor layer includes a first portion facing the second electrode layer in a second direction intersecting with the first direction and a second portion in contact with the first portion in the first direction. A concentration of a impurity contained in the second portion is higher than that of the impurity contained in the first portion.Type: ApplicationFiled: September 1, 2017Publication date: September 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventor: Akio KANEKO
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Publication number: 20180190669Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. A metal layer is provided in contact with at least one of the first and second semiconductor layers. The stacked body, semiconductor layers, insulating layer and metal layer are exposed to an annealing temperature sufficient to cause migration of metal in the metal layer into one of the first and second semiconductor layers.Type: ApplicationFiled: March 1, 2018Publication date: July 5, 2018Inventor: Akio KANEKO
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Patent number: 9929178Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. A metal layer is provided in contact with at least one of the first and second semiconductor layers. The stacked body, semiconductor layers, insulating layer and metal layer are exposed to an annealing temperature sufficient to cause migration of metal in the metal layer into one of the first and second semiconductor layers.Type: GrantFiled: February 1, 2017Date of Patent: March 27, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Akio Kaneko
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Publication number: 20180076213Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. A metal layer is provided in contact with at least one of the first and second semiconductor layers. The stacked body, semiconductor layers, insulating layer and metal layer are exposed to an annealing temperature sufficient to cause migration of metal in the metal layer into one of the first and second semiconductor layers.Type: ApplicationFiled: February 1, 2017Publication date: March 15, 2018Inventor: Akio KANEKO
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Publication number: 20170373082Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.Type: ApplicationFiled: August 22, 2017Publication date: December 28, 2017Applicant: Toshiba Memory CorporationInventors: Katsuyuki SEKINE, Tatsuya KATO, Fumitaka ARAI, Toshiyuki IWAMOTO, Yuta WATANABE, Wataru SAKAMOTO, Hiroshi ITOKAWA, Akio KANEKO
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Publication number: 20170069388Abstract: A nonvolatile memory device includes a conductive layer, a semiconductor layer extending in a first direction on the conductive layer, a first insulating layer provided between the conductive layer and the semiconductor layer, a word line extending in a second direction on the semiconductor layer, the second direction intersecting the first direction, a charge storage layer provided between the semiconductor layer and the word line, and a circuit electrically connected to the conductive layer. The circuit applies an electric potential to the conductive layer when programming data, the electric potential of the conductive layer having the same polarity as an electric potential of the word line.Type: ApplicationFiled: March 11, 2016Publication date: March 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Fumitaka ARAI, Akio KANEKO
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Publication number: 20160071863Abstract: A method of manufacturing a semiconductor storage apparatus according to an embodiment includes forming an array of a plurality of memory cells. The method includes forming an interlayer insulating film that covers the memory cells. The method includes forming a first nitride film that covers an upper part of the interlayer insulating film. The method includes ion-implanting a first impurity into the first nitride film.Type: ApplicationFiled: March 4, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akio KANEKO, Wataru SAKAMOTO, Takeshi MURATA
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Patent number: 9007846Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a memory cell and a control unit. The memory cell has a gate electrode including a control gate and a charge storage region on a semiconductor substrate and has a channel region under the gate electrode in the semiconductor substrate. The control unit, during an erase operation where electric charges written in the charge storage region are extracted to the channel region, periodically varies a voltage which is to be applied between the control gate and the channel region.Type: GrantFiled: February 4, 2013Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Akio Kaneko, Wataru Sakamoto
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Patent number: 8755228Abstract: According to one embodiment, there is provided a writing method. The method includes setting potentials of a plurality of word lines to a first potential. The first potential is a potential to allow memory cells corresponding to a selective bit line to be in on state. The method also includes setting potentials of non-adjacent word lines to a second potential while maintaining potentials of adjacent word lines at a potential which allows the memory cells corresponding to the selective bit line to be in on state and setting a potential of a selective word line to a third potential. The second potential is a potential which is determined so as to allow the memory cells corresponding to the selective bit line to be in off state. The third potential is a potential where data is written in the selective memory cell corresponding to the selective bit line.Type: GrantFiled: February 6, 2013Date of Patent: June 17, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akio Kaneko, Wataru Sakamoto
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Publication number: 20140043917Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a memory cell and a control unit. The memory cell has a gate electrode including a control gate and a charge storage region on a semiconductor substrate and has a channel region under the gate electrode in the semiconductor substrate. The control unit, during an erase operation where electric charges written in the charge storage region are extracted to the channel region, periodically varies a voltage which is to be applied between the control gate and the channel region.Type: ApplicationFiled: February 4, 2013Publication date: February 13, 2014Applicant: Kabushiki Kaisha Toshiba CorporationInventors: Akio KANEKO, Wataru Sakamoto
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Publication number: 20140043909Abstract: According to one embodiment, there is provided a writing method. The method includes setting potentials of a plurality of word lines to a first potential. The first potential is a potential to allow memory cells corresponding to a selective bit line to be in on state. The method also includes setting potentials of non-adjacent word lines to a second potential while maintaining potentials of adjacent word lines at a potential which allows the memory cells corresponding to the selective bit line to be in on state and setting a potential of a selective word line to a third potential. The second potential is a potential which is determined so as to allow the memory cells corresponding to the selective bit line to be in off state. The third potential is a potential where data is written in the selective memory cell corresponding to the selective bit line.Type: ApplicationFiled: February 6, 2013Publication date: February 13, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Akio KANEKO, Wataru SAKAMOTO
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Patent number: 8404575Abstract: A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.Type: GrantFiled: December 6, 2011Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Akio Kaneko, Seiji Inumiya
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Patent number: 8338889Abstract: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.Type: GrantFiled: September 21, 2011Date of Patent: December 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Akio Kaneko, Atsushi Yagishita, Satoshi Inaba
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Publication number: 20120077336Abstract: A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.Type: ApplicationFiled: December 6, 2011Publication date: March 29, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Akio KANEKO, Seiji INUMIYA