Patents by Inventor Akio Kaneko

Akio Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070020901
    Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0?x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.
    Type: Application
    Filed: July 18, 2006
    Publication date: January 25, 2007
    Inventors: Tsunehiro Ino, Akio Kaneko, Nobutoshi Aoki
  • Publication number: 20060275988
    Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask materi
    Type: Application
    Filed: April 17, 2006
    Publication date: December 7, 2006
    Inventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
  • Patent number: 7141466
    Abstract: According to the present invention, there is provided a semiconductor device comprising: an interface insulating film selectively formed on a predetermined region of a semiconductor substrate, and having a film thickness of substantially one atomic layer; a gate insulating film formed on said interface insulating film, and having a dielectric constant higher than that of said interface insulating film; a gate electrode formed on said gate insulating film; and source and drain regions formed in a surface region of said semiconductor substrate on two sides of a channel region positioned below said gate electrode.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: November 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Motoyuki Sato, Kazuhiro Eguchi, Seiji Inumiya, Katsuyuki Sekine, Akio Kaneko
  • Publication number: 20060093731
    Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 4, 2006
    Inventors: Katsuyuki Sekine, Seiji Inumiya, Motoyuki Sato, Akio Kaneko, Kazuhiro Eguchi
  • Publication number: 20060094255
    Abstract: According to the present invention, there is provided a semiconductor device comprising: a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode, wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.
    Type: Application
    Filed: February 4, 2005
    Publication date: May 4, 2006
    Inventors: Katsuyuki Sekine, Akio Kaneko, Motoyuki Sato, Seiji Inumiya, Kazuhiro Eguchi
  • Publication number: 20060057746
    Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a film made of an insulating material on a surface of a semiconductor substrate; measuring a film thickness and/or composition of the film; setting nitriding conditions or oxidation conditions on the basis of the measurement result; and nitriding or oxidizing the film on the basis of the set nitriding conditions or oxidation conditions.
    Type: Application
    Filed: November 12, 2004
    Publication date: March 16, 2006
    Inventors: Seiji Inumiya, Motoyuki Sato, Akio Kaneko, Katsuyuki Sekine, Kazuhiro Eguchi
  • Publication number: 20050236678
    Abstract: According to the present invention, there is provided a semiconductor device comprising: an interface insulating film selectively formed on a predetermined region of a semiconductor substrate, and having a film thickness of substantially one atomic layer; a gate insulating film formed on said interface insulating film, and having a dielectric constant higher than that of said interface insulating film; a gate electrode formed on said gate insulating film; and source and drain regions formed in a surface region of said semiconductor substrate on two sides of a channel region positioned below said gate electrode.
    Type: Application
    Filed: October 13, 2004
    Publication date: October 27, 2005
    Inventors: Motoyuki Sato, Kazuhiro Eguchi, Seiji Inumiya, Katsuyuki Sekine, Akio Kaneko
  • Publication number: 20050170666
    Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a silicate film containing metal on a substrate; and introducing nitrogen and deuterium into the silicate film by using ND3 gas.
    Type: Application
    Filed: December 1, 2004
    Publication date: August 4, 2005
    Inventors: Katsuyuki Sekine, Yoshitaka Tsunashima, Seiji Inumiya, Akio Kaneko, Motoyuki Sato, Kazuhiro Eguchi
  • Publication number: 20050158932
    Abstract: A method of manufacturing a semiconductor device, comprises: providing a gate insulation layer of a high dielectric constant containing a metal element on a surface of a semiconductor substrate, part of which becoming a channel; providing a first conductive layer containing a silicon element on the surface of said gate insulation layer, said first conductive layer being a gate electrode; and introducing nitrogen or oxygen onto an interface between said gate insulation layer and said first conductive layer by executing a thermal treatment upon said semiconductor substrate in a atmosphere containing a nitriding agent or an oxidizing agent.
    Type: Application
    Filed: November 24, 2004
    Publication date: July 21, 2005
    Inventors: Seiji Inumiya, Akio Kaneko, Motoyuki Sato, Katsuyuki Sekine, Kazuhiro Eguchi, Yoshitaka Tsunashima
  • Publication number: 20050110101
    Abstract: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.
    Type: Application
    Filed: August 27, 2004
    Publication date: May 26, 2005
    Inventors: Akio Kaneko, Kazuhiro Eguchi, Seiji Inumiya, Katsuyuki Sekine, Motoyuki Sato
  • Publication number: 20050067704
    Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.
    Type: Application
    Filed: December 18, 2003
    Publication date: March 31, 2005
    Inventors: Akio Kaneko, Seiji Inumiya, Katsuyuki Sekine, Kazuhiro Eguchi, Motoyuki Sato
  • Publication number: 20040169240
    Abstract: A semiconductor device comprises a substrate and a MISFET including source-drain regions formed in the substrate and a gate electrode formed on the substrate with a gate insulating film interposed therebetween. The gate electrode is formed of a metal oxynitride film containing a metal-oxygen-nitrogen bond chain. Alternatively, the gate insulating film is formed of a nitrided metal silicate film containing at least one of a metal-oxygen-nitrogen bond chain and asilicon-oxygen-nitrogen bond chain.
    Type: Application
    Filed: December 4, 2003
    Publication date: September 2, 2004
    Inventors: Masato Koyama, Akira Nishiyama, Yasushi Nakasaki, Masamichi Suzuki, Yuuichi Kamimuta, Akio Kaneko
  • Patent number: 5017710
    Abstract: Fluoran compounds represented by the general formula (I) ##STR1## (where R is an alkyl group having 9 to 12 carbon atoms) and coloring recording materials containing the said compounds as coloring components, and benzoic acid derivatives represented by the general formula (II) ##STR2## (where R is an alkyl group having 9 to 12 carbon atoms).
    Type: Grant
    Filed: October 24, 1989
    Date of Patent: May 21, 1991
    Assignee: Nippon Soda Co., Ltd.
    Inventors: Tetsuo Igaki, Akio Kaneko, Sumio Manaka, Kimiaki Kinoshita
  • Patent number: 4689445
    Abstract: A porcelain electrical insulator resistant to destruction by projectiles comprises a shed and a head portion protrusively and integrally formed with the shed. The thinnest part of the shed is not less than 5 mm, and the thickness of the head portion which is to be covered with a cap or the thickness of the insulator in the vicinity of the junction portion between the head portion and the shed is not less than 2 times the minimum thickness of the shed.
    Type: Grant
    Filed: November 12, 1985
    Date of Patent: August 25, 1987
    Assignee: NGK Insulators, Ltd.
    Inventors: Shoji Seike, Takao Totoki, Akio Kaneko
  • Patent number: 4629561
    Abstract: A liquid chromatograph includes a solvent tank, a pump, a sample injection element, a column, a detector, conduits for successively interconnecting these elements, and a flow controller which is connected between the pump and the detector and in parallel with the column.
    Type: Grant
    Filed: February 20, 1985
    Date of Patent: December 16, 1986
    Assignee: ERMA Optical Works, Ltd.
    Inventors: Kozo Shirato, Kazuo Hiraizumi, Akio Kaneko, Akihiko Nagai
  • Patent number: 4616239
    Abstract: 4-Hydroxy-4'-isopropoxydiphenylsulfone useful as color developer for heat-sensitive color-developable recording material.
    Type: Grant
    Filed: September 16, 1985
    Date of Patent: October 7, 1986
    Assignee: Shin Nisso Kako Co., Ltd.
    Inventors: Masakichi Yahagi, Tetsuo Igaki, Shinji Yoshinaka, Kosaku Morita, Kimiaki Kinoshita, Masashi Enokiya, Akio Kaneko, Toshiyuki Yamashita
  • Patent number: 4568766
    Abstract: 4-Hydroxy-4'-isopropoxydiphenylsulfone useful as color developer for heat-sensitive color-developable recording material.
    Type: Grant
    Filed: June 25, 1984
    Date of Patent: February 4, 1986
    Assignee: Nippon Soda Company Limited
    Inventors: Masakichi Yahagi, Tetsuo Igaki, Shinji Yoshinaka, Kosaku Morita, Kimiaki Kinoshita, Masashi Enokiya, Akio Kaneko, Toshiyuki Yamashita
  • Patent number: 4504968
    Abstract: In a presettable graphic equalizer for use in a car stereo or the like, a display device capable of two-dimensional display is disposed, whereby a frequency characteristic presently given to audio signals can be immediately known from the display of the display device.
    Type: Grant
    Filed: August 5, 1982
    Date of Patent: March 12, 1985
    Assignee: Alps Electric Co., Ltd.
    Inventors: Akio Kaneko, Hitoshi Kajiwara, Yukihiko Haikawa, Kazuya Nishiga
  • Patent number: 4473803
    Abstract: An electronic volume for effecting a control of an impedance circuit in audio devices or the like includes a variable impedance circuit disposed in a signal transmission path and adapted to vary the impedance in accordance with an electronic control signal. A hold/through gate switchable between a hold state and a through state and adapted to permit, when taking the through state, the input signal to pass therethrough in synchronization with a clock signal of a predetermined period and, when taking the hold state, to hold and deliver the input signal as a control signal to the variable impedance circuit, is connected to a control circuit adapted to vary the input signal supplied to the hold/through gate at a predetermined rate at each time of receipt of the hold/through gate, and a rate changing means is provided for changing the rate of variation of the input signal coming through the hold/through gate.
    Type: Grant
    Filed: November 3, 1982
    Date of Patent: September 25, 1984
    Assignee: Alps Electric Co., Ltd.
    Inventors: Akio Kaneko, Hitoshi Kajiwara, Kazuya Nishiga, Yukihiko Haikawa
  • Patent number: 4464781
    Abstract: An equalizer apparatus for audio equipment capable of selecting between a 2-speaker system and a 4-speaker system, including a display device indicating proper operation of the control knobs of the equalizer. The display device includes a first illuminable element of a first color for indicating operation of one channel of stereophonic sound reproduction, a second illuminable element of a second color for indicating operation of the other channel of stereophonically reproduced sound, and color coded means corresponding to said first and second colors for indicating which of the control knobs produce data signals for the first channel and which of the control knobs produce data signals for the second channel. Further, the color coded means may indicate which of the control knobs produce data signals for each of the divided frequencies of the respective channels during operation of the audio equipment in the manner simulating quadriphonic sound.
    Type: Grant
    Filed: July 9, 1981
    Date of Patent: August 7, 1984
    Assignee: Alps Electric Co., Ltd.
    Inventors: Akio Kaneko, Hitoshi Kajiwara