Patents by Inventor Akira Fujimoto

Akira Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9318661
    Abstract: A semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a first electrode layer, a light emitting layer, a second semiconductor layer, a third semiconductor layer and a second electrode layer. The first electrode layer includes a metal portion having a plurality of opening portions. The opening portions penetrate the metal portion and have an equivalent circle diameter of a shape of the opening portions. The light emitting layer is between the first semiconductor layer and the first electrode layer. The second semiconductor layer of a second conductivity type is between the light emitting layer and the first electrode layer. The third semiconductor layer of a second conductivity type is between the second semiconductor layer and the first electrode layer. The second electrode layer is connected to the first semiconductor layer.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: April 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kumi Masunaga, Ryota Kitagawa, Eishi Tsutsumi, Akira Fujimoto, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Patent number: 9312407
    Abstract: The present invention provides a metal electrode transparent to light. The metal electrode comprises a transparent substrate and a metal electrode layer composed of a metal part and plural openings. The metal electrode layer continues without breaks, and 90% or more of the metal part continues linearly without breaks by the openings in a straight length of not more than ? of the visible wavelength to use in 380 nm to 780 nm. The openings have an average diameter in the range of not less than 10 nm and not more than ? of the wavelength of incident light, and the pitches between the centers of the openings are not less than the average diameter and not more than ½ of the wavelength of incident light. The metal electrode layer has a thickness in the range of not less than 10 nm and not more than 200 nm.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: April 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Eishi Tsutsumi, Akira Fujimoto, Koji Asakawa
  • Publication number: 20160035382
    Abstract: According to one embodiment, a magnetic recording medium includes an orientation control layer formed on a non-magnetic substrate, the orientation control layer made of a Ni alloy or Ag alloy having fcc structure, a non-magnetic seed layer made of Ag, Ge, and a metal X selected from the group consisting of Al, Mg, Au, and Ti, a non-magnetic intermediate layer made of Ru or Ru alloy, and a magnetic recording layer. The orientation control layer is in contact with the non-magnetic seed layer.
    Type: Application
    Filed: October 14, 2014
    Publication date: February 4, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi IWASAKI, Akira Fujimoto
  • Patent number: 9231132
    Abstract: A solar cell having on a light incident surface side an electrode with both low resistivity and high transparency to promote efficient excitation of carriers using inexpensive materials. The solar cell includes a photoelectric conversion layer, a first electrode layer arranged on the light incident surface side, and a second electrode layer arranged opposed to the first electrode layer. The first electrode layer has a thickness in the range of 10 to 200 nm, and plural penetrating openings, each of which occupies an area in the range of 80 nm2 to 0.8 ?m2, and has an aperture ratio in the range 10 to 66%. The first electrode layer can be produced by etching using an etching mask in the form of a single particle layer of fine particles, or of a dot pattern formed by self-assembly of a block copolymer, or of a stamper.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumi Masunaga, Akira Fujimoto, Tsutomu Nakanishi, Eishi Tsutsumi, Ryota Kitagawa, Koji Asakawa, Hideyuki Nishizawa
  • Patent number: 9177989
    Abstract: A solid state imaging device according to an embodiment includes a photo detector arranged two-dimensionally in a semiconductor substrate, a readout circuit provided in the semiconductor substrate, a first photoelectric conversion layer provided above the photo detector, a plurality of first metal dots provided above the first photoelectric conversion layer, a second photoelectric conversion layer provided above the first metal dots, and a plurality of second metal dots provided above the second photoelectric conversion layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 3, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ikuo Fujiwara, Hideyuki Funaki, Kenji Todori, Akira Fujimoto, Tsutomu Nakanishi, Kenji Nakamura
  • Publication number: 20150310885
    Abstract: According to one embodiment, disclosed is a pattern forming method including preparing a second dispersion by adding a second protective group and second solvent to fine particles including a first protective group whose surface polarity is close to that of the substrate, the fine particles containing, at least on the surface thereof, a material selected from Al, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Sn, Mo, Ta, W, Au, Ag, Pd, Cu, Pt, and an oxide thereof, modifying the fine particles including the first protective group with the second protective group, adding a viscosity adjustment agent to the dispersion containing the fine particles to prepare a coating solution, and applying the coating solution on the substrate to form a fine particle layer thereon.
    Type: Application
    Filed: August 8, 2014
    Publication date: October 29, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kaori Kimura, Akira Fujimoto, Akira Watanabe
  • Publication number: 20150311393
    Abstract: According to one embodiment, a semiconductor light emitting device includes a structure, a first electrode layer, and a second electrode layer. The structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode layer is provided on the first semiconductor layer side of the structure. The first electrode layer is made of metal and contains a portion contacting the first semiconductor layer. The second electrode layer is provided on the second semiconductor layer side of the structure. The second electrode layer has a metal portion with a thickness of not less than 10 nanometers and not more than 50 nanometers, and a plurality of openings piercing the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers.
    Type: Application
    Filed: June 17, 2015
    Publication date: October 29, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji ASAKAWA, Akira FUJIMOTO, Ryota KITAGAWA, Kumi MASUNAGA, Takanobu KAMAKURA, Shinji NUNOTANI
  • Patent number: 9165588
    Abstract: According to one embodiment, a magnetic recording layer is coated with a fine particle coating solution containing fine particles coated with a protective layer containing a first additive including a straight-chain structure for increasing wettability to the magnetic recording layer, and a carboxy group or the like, and a second additive including a carboxy group or the like and a polymerizable functional group, each fine particle having, on at least a surface thereof, a material selected from Al, Si, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Sn, Mo, Ta, W, and oxides thereof, thereby forming a fine particle monolayer, and heat or light energy is applied, thereby curing the protective layer and forming a periodic pattern.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: October 20, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kaori Kimura, Kazutaka Takizawa, Akira Fujimoto
  • Patent number: 9159880
    Abstract: According to one embodiment, a semiconductor light emitting device includes a structure, a first electrode layer, and a second electrode layer. The structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode layer is provided on the first semiconductor layer side of the structure. The first electrode layer is made of metal and contains a portion contacting the first semiconductor layer. The second electrode layer is provided on the second semiconductor layer side of the structure. The second electrode layer has a metal portion with a thickness of not less than 10 nanometers and not more than 50 nanometers, and a plurality of openings piercing the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Akira Fujimoto, Ryota Kitagawa, Kumi Masunaga, Takanobu Kamakura, Shinji Nunotani
  • Patent number: 9153363
    Abstract: The present invention provides a light-transmitting metal electrode including a substrate and a metal electrode layer having plural openings. The metal electrode layer also has such a continuous metal part that any pair of point-positions in the part is continuously connected without breaks. The openings in the metal electrode layer are periodically arranged to form plural microdomains. The plural microdomains are so placed that the in-plane arranging directions thereof are oriented independently of each other. The thickness of the metal electrode layer is in the range of 10 to 200 nm.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eishi Tsutsumi, Tsutomu Nakanishi, Akira Fujimoto, Koji Asakawa
  • Patent number: 9142728
    Abstract: According to one embodiment, a semiconductor light emitting device includes a structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes an electrode layer provided on the second semiconductor layer side of the structure. The electrode layer includes a metal portion with a thickness of not less than 10 nanometers and not more than 100 nanometers. A plurality of openings pierces the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers. The device includes an inorganic film providing on the metal portion and inner surfaces of the openings, the inorganic film having transmittivity with respect to light emitted from the light emitting layer.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: September 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Ryota Kitagawa, Kumi Masunaga, Kenji Nakamura, Tsutomu Nakanishi, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Patent number: 9136405
    Abstract: The present invention provides a light transmission type solar cell excellent in both power generation efficiency and light transparency, and also provides a method for producing that solar cell. The solar cell of the present invention comprises a photoelectric conversion layer, a light-incident side electrode layer, and a counter electrode layer. The incident side electrode layer is provided with plural openings bored through the layer, and has a thickness of 10 nm to 200 nm. Each of the openings occupies an area of 80 nm2 to 0.8 ?m2, and the opening ratio is in the range of 10% to 66%. The transmittance of the whole cell is 5% or more at 700 nm wavelength. The incident side electrode layer can be formed by etching fabrication with a stamper. In the etching fabrication, a mono-particle layer of fine particles or a dot pattern formed by self-assembled block copolymer can be used as a mask.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: September 15, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Eishi Tsutsumi, Kumi Masunaga, Ryota Kitagawa, Tsutomu Nakanishi, Akira Fujimoto, Hideyuki Nishizawa, Koji Asakawa
  • Publication number: 20150162042
    Abstract: According to one embodiment, a perpendicular magnetic recording medium includes a substrate, an underlayer formed on the substrate and a magnetic recording layer formed on the underlayer and having an easy axis in a direction perpendicular to a film surface. The underlayer includes a plurality of projecting portions arranged at a distance of 1 nm to 20 nm from one another. The magnetic recording layer is an amorphous magnetic recording layer including a plurality of magnetic grains each formed to expand towards a top end thereof from a surface of a respective projecting portion of the underlayer, at least those of the magnetic grains located on a respective projecting portion side being separated from each other.
    Type: Application
    Filed: September 25, 2014
    Publication date: June 11, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kaori Kimura, Soichi Oikawa, Kazutaka Takizawa, Akira Fujimoto, Akihiko Takeo
  • Patent number: 9040324
    Abstract: A semiconductor light-emitting device according to the embodiment includes a substrate, a compound semiconductor layer, a metal electrode layer provided with particular openings, a light-extraction layer, and a counter electrode. The light-extraction layer has a thickness of 20 to 120 nm and covers at least partly the metal part of the metal electrode layer; or otherwise the light-extraction layer has a rugged structure and covers at least partly the metal part of the metal electrode layer. The rugged structure has projections so arranged that their summits are positioned at intervals of 100 to 600 nm, and the heights of the summits from the surface of the metal electrode layer are 200 to 700 nm.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Ryota Kitagawa, Eishi Tsutsumi, Koji Asakawa
  • Patent number: 8993869
    Abstract: A photoelectric conversion element includes a photoelectric conversion layer to include a first metal layer, a semiconductor layer, and a second metal layer, all of which are laminated. In addition, at least one of the first metal layer and the second metal layer is a nano-mesh metal having a plurality of through holes or a dot metal having a plurality of metal dots arranged separately from each other on the semiconductor layer. The photoelectric conversion layer includes a long-wavelength absorption layer containing an impurity which is different from impurities for p-type doping and n-type doping of the semiconductor layer. The long-wavelength absorption layer is within a depth of 5 nm from the nano-mesh metal or the dot metal.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Tsutomu Nakanishi, Kenji Nakamura, Kumi Masunaga, Koji Asakawa
  • Publication number: 20150083211
    Abstract: The present disclosure provides a photoelectric conversion layer containing a semiconductor and plural metal-containing minute structures dispersed therein. The minute structures are minute structures (A) comprising metal material (?) or otherwise minute structures (B) comprising metal material (?) and material (?) selected from the group consisting of oxide, nitride and oxynitride of substances and the semiconductor. In the minute structures (B), the material (?) is on the surface of the metal material (?). Each of the minute structures has an equivalent circle diameter of 1 nm to 10 nm inclusive on the basis of the projected area when observed from a particular direction. The closest distance between adjacent two of the minute structures is 3 nm to 50 nm inclusive. The present disclosure also provides applications of the photoelectric conversion layer to a solar cell, a photodiode and an image sensor.
    Type: Application
    Filed: September 17, 2014
    Publication date: March 26, 2015
    Inventors: Akira FUJIMOTO, Takeshi IWASAKI, Kaori KIMURA, Kazutaka TAKIZAWA, Kenji NAKAMURA, Shigeru MATAKE
  • Publication number: 20150083205
    Abstract: The present disclosure provides a photoelectric conversion element comprising a photoelectric conversion layer laminated a first metal layer, a first semiconductor layer, a second semiconductor layer and a second metal layer. The first or second metal layer contains a porous metal thin film, and the porous metal thin film has plural openings penetrating through the film. Each of the openings has an area of 80 nm2 to 0.8 ?m2 inclusive on average, and the porous metal thin film has a thickness of 2 nm to 200 nm inclusive. The second semiconductor layer has a smaller band gap than the first semiconductor layer, has polarity opposite to that of the first semiconductor layer, and is positioned within 5 nm from the porous metal thin film.
    Type: Application
    Filed: September 17, 2014
    Publication date: March 26, 2015
    Inventors: Akira FUJIMOTO, Tsutomu NAKANISHI, Kenji NAKAMURA
  • Publication number: 20150072456
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes a first electrode layer having electrical continuity with the first semiconductor layer and a second electrode layer provided on the second semiconductor layer, the second electrode layer including a metal portion having a thickness not less than 10 nanometers and not more than 100 nanometers along a direction from the first semiconductor layer to the second semiconductor layer.
    Type: Application
    Filed: November 18, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kumi MASUNAGA, Ryota Kitagawa, Akira Fujimoto, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Publication number: 20150069013
    Abstract: According to one embodiment, a magnetic recording layer is coated with a fine particle coating solution containing fine particles coated with a protective layer containing a first additive including a straight-chain structure for increasing wettability to the magnetic recording layer, and a carboxy group or the like, and a second additive including a carboxy group or the like and a polymerizable functional group, each fine particle having, on at least a surface thereof, a material selected from Al, Si, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Sn, Mo, Ta, W, and oxides thereof, thereby forming a fine particle monolayer, and heat or light energy is applied, thereby curing the protective layer and forming a periodic pattern.
    Type: Application
    Filed: January 10, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kaori KIMURA, Kazutaka TAKIZAWA, Akira FUJIMOTO
  • Publication number: 20150069014
    Abstract: According to one embodiment, there is provided a pattern formation method including coating a substrate or mask layer with a fine particle coating solution containing fine particles including a protective group having a close surface polarity and containing, on at least surfaces thereof, a material selected from the group consisting of Al, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Sn, Mo, Ta, W, Au, Ag, Pd, Cu, Pt and oxides thereof, a viscosity modifier, and a solvent for adjusting mixing of the viscosity modifier and the fine particles having the protective group to form a fine particle layer on the substrate or mask layer.
    Type: Application
    Filed: July 7, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kaori KIMURA, Kazutaka TAKIZAWA, Akira FUJIMOTO