Patents by Inventor Akira Fujimoto

Akira Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150069014
    Abstract: According to one embodiment, there is provided a pattern formation method including coating a substrate or mask layer with a fine particle coating solution containing fine particles including a protective group having a close surface polarity and containing, on at least surfaces thereof, a material selected from the group consisting of Al, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Sn, Mo, Ta, W, Au, Ag, Pd, Cu, Pt and oxides thereof, a viscosity modifier, and a solvent for adjusting mixing of the viscosity modifier and the fine particles having the protective group to form a fine particle layer on the substrate or mask layer.
    Type: Application
    Filed: July 7, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kaori KIMURA, Kazutaka TAKIZAWA, Akira FUJIMOTO
  • Publication number: 20150072071
    Abstract: According to one embodiment, there is provided a pattern formation method including coating a substrate or mask layer with a fine particle coating solution containing fine particles including a protective group having a close surface polarity and containing, on at least surfaces thereof, a material selected from the group consisting of Al, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Sn, Mo, Ta, W, and oxides thereof, a viscosity modifier, and a solvent for adjusting mixing of the viscosity modifier and the fine particles having the protective group, thereby forming a fine particle layer on the substrate or mask layer.
    Type: Application
    Filed: January 27, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kaori KIMURA, Kazutaka Takizawa, Akira Fujimoto
  • Patent number: 8941158
    Abstract: Certain embodiments provide a solid-state imaging device including: a semiconductor substrate of a first conductivity type having a first face and a second face that is the opposite side from the first face; a plurality of pixels provided on the first face of the semiconductor substrate, each of the pixels including a semiconductor region of a second conductivity type that converts incident light into signal charges, and stores the signal charges; a readout circuit provided on the second face of the semiconductor substrate to read the signal charges stored in the pixels; an ultrafine metal structure placed at intervals on a face on a side of the semiconductor region, the light being incident on the face; and an insulating layer provided between the ultrafine metal structure and the semiconductor region.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Iida, Eishi Tsutsumi, Akira Fujimoto, Koji Asakawa, Hisayo Momose, Koichi Kokubun, Nobuyuki Momo
  • Patent number: 8921887
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes a first electrode layer having electrical continuity with the first semiconductor layer and a second electrode layer provided on the second semiconductor layer, the second electrode layer including a metal portion having a thickness not less than 10 nanometers and not more than 100 nanometers along a direction from the first semiconductor layer to the second semiconductor layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kumi Masunaga, Ryota Kitagawa, Akira Fujimoto, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Publication number: 20140349421
    Abstract: According to one embodiment, a semiconductor light emitting device includes a structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes an electrode layer provided on the second semiconductor layer side of the structure. The electrode layer includes a metal portion with a thickness of not less than 10 nanometers and not more than 100 nanometers. A plurality of openings pierces the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers. The device includes an inorganic film providing on the metal portion and inner surfaces of the openings, the inorganic film having transmittivity with respect to light emitted from the light emitting layer.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira FUJIMOTO, Ryota KITAGAWA, Kumi MASUNAGA, Kenji NAKAMURA, Tsutomu NAKANISHI, Koji ASAKAWA, Takanobu KAMAKURA, Shinji NUNOTANI
  • Patent number: 8853711
    Abstract: A semiconductor light emitting device includes a structural body, a first electrode layer, an intermediate layer and a second electrode layer. The structural body includes a first semiconductor layer of first conductivity type, a second semiconductor layer of second conductivity type, and a light emitting layer between the first and second semiconductor layers. The first electrode layer is on a side of the second semiconductor layer opposite to the first semiconductor layer; the first electrode layer includes a metal portion and plural opening portions piercing the metal portion along a direction from the first semiconductor layer toward the second semiconductor layer, having an equivalent circular diameter not less than 10 nanometers and not more than 5 micrometers. The intermediate layer is between the first and second semiconductor layers in ohmic contact with the second semiconductor layer. The second electrode layer is electrically connected to the first semiconductor layer.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Koji Asakawa, Ryota Kitagawa, Takanobu Kamakura, Shinji Nunotani, Eishi Tsutsumi, Masaaki Ogawa
  • Patent number: 8840258
    Abstract: The present invention provides such a formation method that an antireflection structure having excellent antireflection functions can be formed in a large area and at small cost. Further, the present invention also provides an antireflection structure formed by that method. In the formation method, a base layer and particles placed thereon are subjected to an etching process. The particles on the base layer serve as an etching mask in the process, and hence they are more durable against etching than the base layer. The etching rate ratio of the base layer to the particles is more than 1 but not more than 5. The etching process is stopped before the particles disappear. It is also possible to produce an antireflection structure by nanoimprinting method employing a stamper. The stamper is formed by use of a master plate produced according to the above formation method.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakanishi, Akira Fujimoto, Koji Asakawa, Takeshi Okino, Shinobu Sugimura
  • Patent number: 8835954
    Abstract: According to one embodiment, a semiconductor light emitting device includes a structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes an electrode layer provided on the second semiconductor layer side of the structure. The electrode layer includes a metal portion with a thickness of not less than 10 nanometers and not more than 100 nanometers. A plurality of openings pierces the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers. The device includes an inorganic film providing on the metal portion and inner surfaces of the openings, the inorganic film having transmittivity with respect to light emitted from the light emitting layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Ryota Kitagawa, Kumi Masunaga, Kenji Nakamura, Tsutomu Nakanishi, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Publication number: 20140182677
    Abstract: A photoelectric conversion element according to an embodiments includes: a first metal layer; a semiconductor layer formed on the first metal layer; a second metal layer formed on the semiconductor layer, the second metal layer comprising a porous thin film with a plurality of openings each having a mean area not smaller than 80 nm2 and not larger than 0.8 ?m2 or miniature structures having a mean volume not smaller than 4 nm3 and not larger than 0.52 ?m3; and a wavelength converting layer formed between the semiconductor layer and the second metal layer, at least a refractive index of a portion of the wavelength converting layer being lower than a refractive index of a material of the semiconductor layer, the portion being at a distance of 5 nm or shorter from an end portion of the second metal layer.
    Type: Application
    Filed: March 10, 2014
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akira FUJIMOTO, Eishi Tsutsumi, Tsutomu Nakanishi, Kumi Masunaga, Kenji Nakamura, Koji Asakawa
  • Patent number: 8754431
    Abstract: According to one embodiment, a semiconductor light emitting device includes first and second electrode layers, a and second semiconductor layers, a light emitting layer and a first intermediate layer. The first electrode layer has a metal portion having through-holes. The second electrode layer is stacked with the first electrode layer along a stacked direction, and light-reflective. The first semiconductor layer is provided between the first and second electrode layers, and has a first conductivity type. The second semiconductor layer is provided between the first semiconductor layer and the second electrode layer, and has a second conductivity type. The light emitting layer is provided between the first and second semiconductor layers. The first intermediate layer is provided between the second semiconductor layer and the second electrode layer, transmissive to light emitted from the light emitting layer, and includes first contact portions and a first non-contact portion.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Tsutomu Nakanishi, Ryota Kitagawa, Kenji Nakamura, Shinji Nunotani, Takanobu Kamakura
  • Publication number: 20140151326
    Abstract: The present invention provides a light-transmitting metal electrode including a substrate and a metal electrode layer having plural openings. The metal electrode layer also has such a continuous metal part that any pair of point-positions in the part is continuously connected without breaks. The openings in the metal electrode layer are periodically arranged to form plural microdomains. The plural microdomains are so placed that the in-plane arranging directions thereof are oriented independently of each other. The thickness of the metal electrode layer is in the range of 10 to 200 nm.
    Type: Application
    Filed: February 6, 2014
    Publication date: June 5, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Eishi Tsutsumi, Tsutomu Nakanishi, Akira Fujimoto, Koji Asakawa
  • Publication number: 20140145232
    Abstract: A semiconductor light-emitting device according to the embodiment includes a substrate, a compound semiconductor layer, a metal electrode layer provided with particular openings, a light-extraction layer, and a counter electrode. The light-extraction layer has a thickness of 20 to 120 nm and covers at least partly the metal part of the metal electrode layer; or otherwise the light-extraction layer has a rugged structure and covers at least partly the metal part of the metal electrode layer. The rugged structure has projections so arranged that their summits are positioned at intervals of 100 to 600 nm, and the heights of the summits from the surface of the metal electrode layer are 200 to 700 nm.
    Type: Application
    Filed: January 30, 2014
    Publication date: May 29, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Ryota Kitagawa, Eishi Tsutsumi, Koji Asakawa
  • Publication number: 20140139714
    Abstract: A solid state imaging device according to an embodiment includes a photo detector arranged two-dimensionally in a semiconductor substrate, a readout circuit provided in the semiconductor substrate, a first photoelectric conversion layer provided above the photo detector, a plurality of first metal dots provided above the first photoelectric conversion layer, a second photoelectric conversion layer provided above the first metal dots, and a plurality of second metal dots provided above the second photoelectric conversion layer.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 22, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ikuo FUJIWARA, Hideyuki FUNAKI, Kenji TODORI, Akira FUJIMOTO, Tsutomu NAKANISHI, Kenji NAKAMURA
  • Patent number: 8692283
    Abstract: According to one embodiment, a light-transmitting metal electrode includes a metal layer. The metal layer is provided on a major surface of a member and includes a metal nanowire and a plurality of openings formed with the metal nanowire. The thin layer includes a plurality of first straight line parts along a first direction and a plurality of second straight line parts along a direction different from the first direction. A maximum length of the first line parts along the first direction and a maximum length of the second line parts along the direction different from the first direction are not more than a wave length of visible light. A ratio of an area of the metal layer viewed in a normal direction of the surface to an area of the metal layer viewed in the normal direction is more than 20% and not more than 80%.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: April 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakanishi, Akira Fujimoto, Ryota Kitagawa, Kumi Masunaga, Kenji Nakamura, Koji Asakawa, Shinji Nunotani, Takanobu Kamakura
  • Patent number: 8686459
    Abstract: The present invention provides a light-transmitting metal electrode including a substrate and a metal electrode layer having plural openings. The metal electrode layer also has such a continuous metal part that any pair of point-positions in the part is continuously connected without breaks. The openings in the metal electrode layer are periodically arranged to form plural microdomains. The plural microdomains are so placed that the in-plane arranging directions thereof are oriented independently of each other. The thickness of the metal electrode layer is in the range of 10 to 200 nm.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: April 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eishi Tsutsumi, Tsutomu Nakanishi, Akira Fujimoto, Koji Asakawa
  • Patent number: 8680561
    Abstract: A semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a light emitting layer, a first electrode layer, and a second electrode layer. The light emitting layer is between the first semiconductor layer and the second semiconductor layer. The first electrode layer is on a side of the second semiconductor layer opposite to the first semiconductor layer. The first electrode layer includes a metal portion and a plurality of opening portions piercing the metal portion along a direction from the first semiconductor layer toward the second semiconductor layer. The metal portion contacts the second semiconductor layer. An equivalent circular diameter of a configuration of the opening portions as viewed along the direction is not less than 10 nanometers and not more than 5 micrometers.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Kitagawa, Akira Fujimoto, Koji Asakawa, Eishi Tsutsumi, Takanobu Kamakura, Shinji Nunotani, Masaaki Ogawa
  • Patent number: 8680549
    Abstract: A semiconductor light-emitting device according to the embodiment includes a substrate, a compound semiconductor layer, a metal electrode layer provided with particular openings, a light-extraction layer, and a counter electrode. The light-extraction layer has a thickness of 20 to 120 nm and covers at least partly the metal part of the metal electrode layer; or otherwise the light-extraction layer has a rugged structure and covers at least partly the metal part of the metal electrode layer. The rugged structure has projections so arranged that their summits are positioned at intervals of 100 to 600 nm, and the heights of the summits from the surface of the metal electrode layer are 200 to 700 nm.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Ryota Kitagawa, Eishi Tsutsumi, Koji Asakawa
  • Patent number: 8659040
    Abstract: One aspect of the present invention provides a semiconductor light-emitting device improved in luminance, and also provides a process for production thereof. The process comprises a procedure of forming a relief structure on the light-extraction surface of the device by use of a self-assembled film. In that procedure, the light-extraction surface is partly covered with a protective film so as to protect an area for an electrode to be formed therein. The electrode is then finally formed there after the procedure. The process thus reduces the area incapable, due to thickness of the electrode, of being provided with the relief structure. Between the electrode and the light-extraction surface, a contact layer is formed so as to establish ohmic contact between them.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Ryota Kitagawa, Koji Asakawa, Hidefumi Yasuda, Yasuhiko Akaike, Takeyuki Suzuki
  • Publication number: 20140024165
    Abstract: A solar cell having on a light incident surface side an electrode with both low resistivity and high transparency to promote efficient excitation of carriers using inexpensive materials. The solar cell includes a photoelectric conversion layer, a first electrode layer arranged on the light incident surface side, and a second electrode layer arranged opposed to the first electrode layer. The first electrode layer has a thickness in the range of 10 to 200 nm, and plural penetrating openings, each of which occupies an area in the range of 80 nm2 to 0.8 ?m2, and has an aperture ratio in the range 10 to 66%. The first electrode layer can be produced by etching using an etching mask in the form of a single particle layer of fine particles, or of a dot pattern formed by self-assembly of a block copolymer, or of a stamper.
    Type: Application
    Filed: September 27, 2013
    Publication date: January 23, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kumi MASUNAGA, Akira Fujimoto, Tsutomu Nakanishi, Eishi Tsutsumi, Ryota Kitagawa, Koji Asakawa, Hideyuki Nishizawa
  • Patent number: 8628673
    Abstract: Disclosed are: a resin composition for pattern formation, which enables the stable formation of a pattern at a level of the wavelength of light; a method for forming a pattern having a sea-island structure using the composition; and a process for producing a light-emitting element that can achieve high luminous efficiency properties.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: January 14, 2014
    Assignees: Kabushiki Kaisha Toshiba, Asahi Kasei E-Materials Corporation
    Inventors: Koji Asakawa, Ryota Kitagawa, Akira Fujimoto, Yoshiaki Shirae, Tomohiro Yorisue, Akihiko Ikeda