Abstract: Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.

Abstract: Systems for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include a device configured to determine an initial mask pattern from a desired pattern for a substrate; a device configured to calculate a first substrate pattern from the initial mask pattern; a device configured to determine an initial set of VSB shots based on the initial mask pattern; a device configured to calculate a second substrate pattern from a simulated mask pattern calculated with the initial set of VSB shots; a device configured to compare the first substrate pattern with the second substrate pattern; and a device configured to adjust the initial set of VSB shots until the second substrate pattern and the first substrate pattern are within a predetermined tolerance, creating an adjusted set of VSB shots.

Abstract: Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).

Abstract: Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).

Abstract: Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).

Abstract: Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).

Abstract: Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).

Abstract: Methods incorporate variable side wall angle (VSA) into calculated patterns, using a mask 3D (M3D) effect. Embodiments include inputting a mask exposure information and determining the M3D effect. Determining the M3D effect may include determining the VSA. Embodiments may include calculating a VSA; and calculating a pattern on a substrate using the calculated VSA, wherein calculating the pattern on the substrate includes a mask 3D effect.

Abstract: Some embodiments provide a method for optimizing a mask layout generated from a design layout of an IC. Based on an initial mask layout for a first layer, the method generates a simulated wafer image including shapes representing IC components of the layer, including a first component that has a relationship with a second component on a second layer of the design layout. The method identifies, in the simulated wafer image, (i) a first set of regions of a first shape of the first component that overlap with a second shape of the second component and (ii) a second set of regions of the first shape that do not overlap with the second shape. To improve overlap between the first shape's first set of regions and the second shape, the method modifies the initial mask layout to produce a modified mask layout.

Abstract: Methods and systems for fracturing a pattern to be exposed on a surface using variable shaped beam (VSB) lithography include inputting an initial pattern; calculating a first substrate pattern from the initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by a union of the initial pattern with locations on the grid; and merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots. The methods and systems also include calculating a calculated pattern to be exposed on the surface with the modified set of VSB shots; and calculating a second substrate pattern from the calculated pattern to be exposed on the surface.

Abstract: Methods and systems for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area, based on an original set of exposure information. A pre-proximity effect correction (PEC) maximum dose for the local pattern density is determined, based on a pre-determined target post-PEC maximum dose. The pre-PEC maximum dose may be calculated near an edge of the desired shape. Methods also include modifying the original set of exposure information with the pre-PEC maximum dose to create a modified set of exposure information.

Abstract: Some embodiments provide a method for optimizing a mask layout for producing masks for manufacturing an integrated circuit (IC) by defining multiple layers of components on a substrate. The method generates, based on a first mask layout, a simulated wafer image including representations of IC components that are predicted to be manufactured for a first layer of the IC based on a received mask layout for the first layer. The method compares the simulated wafer image to a target wafer image including optimal representations of the IC components for the first layer. The comparison uses data regarding locations of components in at least one additional layer that interact with components in the first layer. Based on the comparison, the method modifies the first mask layout to generate a modified second mask layout for the first layer.

Abstract: Some embodiments provide a method for performing an electronic design automation (EDA) operation with respect to a circuit component that is defined on a layer of an EDA design layout. The layer is defined by (i) a plane defined along x- and y-axes and (ii) having a thickness along a z-axis. The method uses a wafer shape simulator to generate multiple two dimensional (2-D) shapes for the circuit component with each 2D shape representing a different predicted manufactured cross x-y section of the component at a different location along the z-axis. The method uses the 2-D shapes to generate, for the circuit component, a predicted-as-manufactured three dimensional (3-D) shape that deviates along the z-axis. The method performs an EDA operation for the circuit component using the predicted-as-manufactured 3-D shape.

Abstract: Some embodiments provide a method for optimizing a mask layout for producing masks that are used for manufacturing an integrated circuit (IC) comprising multiple layers of components. The method receives a mask layout including a set of mask images corresponding to a first layer of components of the IC that is adjacent to at least a second layer of components. The method generates a first wafer image including representations of IC components that are predicted to be manufactured for the first layer based on the received set of mask images corresponding to the first layer. Based on a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image for the second layer, the method modifies at least one mask image in the set of mask images for the first layer.

Abstract: Some embodiments provide a method for modifying a mask layout for producing masks used to manufacture an IC. The method identifies a first set of mask images corresponding to a first layer and a second set of mask images corresponding to a second layer. The method formulates a problem that expresses correlation between desired shapes of IC components and predicted as-manufactured shapes of the IC components. The IC components include components on the first layer and vias on the second layer, each via connecting a first-layer component to a component on another layer. The method solves the problem by iteratively exploring modifications to both the first and second sets of mask images to identify modified sets of mask images that result in predicted as-manufactured shapes for the components on the first layer and the vias on the second layer that sufficiently correlate to the desired shapes of the IC components.

Abstract: Some embodiments provide a method for performing parasitic extraction for a layer of a design layout of an integrated circuit (IC). The design layout includes a set of conductive circuit components that traverse within a plane defined for the layer. The method identifies, for a particular conductive circuit component, multiple different three-dimensional (3-D) shapes that have different variations in a direction orthogonal to the plane based on different sets of manufacturing process conditions. The method uses the different 3-D shapes to compute a set of parasitic values for the particular conductive circuit component that express parasitic effects affecting the particular conductive circuit component in the IC.

Abstract: Some embodiments provide a method for performing parasitic extraction. The method identifies first and second conductive circuit components on a layer of a design layout for an integrated circuit (IC). The first and second conductive circuit components (i) traverse within a plane defined for the layer and (ii) have a thickness orthogonal to the plane. The method identifies, for each conductive circuit component, a predicted manufactured three-dimensional (3-D) shape of the conductive circuit component. At least one of the identified shapes tapers in the direction orthogonal to the plane. The method uses the identified 3-D shapes of the first and second conductive circuit components to compute a parasitic effect of the second conductive component on the first conductive component.

Abstract: Some embodiments provide a method for optimizing a mask layout generated from a design layout of an IC. Based on an initial mask layout for a first layer, the method generates a simulated wafer image including shapes representing components of the first layer, including a first component that overlaps with a second component on a second layer. The method identifies a more critical first region and a less critical second region of a first shape of the first component that both overlap with a second shape of the second component. The more critical first region is more important to ensuring overlap of the first shape with the second shape. To improve overlap between the first and second shapes, the method uses different costs for the more critical first region and the less critical second region to modify the initial mask layout to produce a modified mask layout.

Abstract: Some embodiments provide a method for performing an electronic design automation (EDA) operation with respect to a circuit component that is defined on a layer of an EDA design layout. The layer is defined by (i) a plane defined along x- and y-axes and (ii) a thickness along a z-axis. Based on the layer of the design layout, the method uses a wafer shape simulator to directly generate a predicted three dimensional (3-D) shape that represents a predicted manufactured shape of the component. The predicted 3-D shape has tapered sides that are offset from the z-axis based on a manufacturing process used to manufacture the circuit component that results in non-parallel sides of the component. The method performs an EDA operation for the circuit component using the generated 3-D shape.

Abstract: Some embodiments provide a method for optimizing a mask layout generated from a design layout of an integrated circuit (IC). The method generates, based on a first mask layout, a simulated wafer image having predicted manufactured shapes representing IC components that are to be manufactured on a first layer of the IC. The method identifies a cross-sectional overlap between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC. The first and second IC components are related components in the IC. Based on the cross-sectional overlap, the method modifies the first mask layout to generate a modified second mask layout for the first layer.