Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Methods incorporate variable side wall angle (VSA) into calculated patterns, using a mask 3D (M3D) effect. Embodiments include inputting a mask exposure information, calculating a mask 2D (M2D) effect from the mask exposure information, and determining the M3D effect from the M2D effect. Determining the M3D effect may include determining the VSA, such as by using a neural network. Embodiments may include determining a dose margin from mask exposure information; calculating a VSA using the dose margin; and calculating a pattern on a substrate using the calculated VSA, wherein calculating the pattern on the substrate includes a mask 3D effect.

Abstract: Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Abstract: Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Abstract: Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.

Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information including the dosages for the plurality of pixels in the area. An increase in dosage for at least one pixel in a plurality of pixels in the sub area is determined, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area.

Abstract: Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Abstract: Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.

Abstract: A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.

Abstract: A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.

Abstract: A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.

Abstract: A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.

Abstract: Methods for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area, based on an original set of exposure information. A pre-proximity effect correction (PEC) maximum dose for the local pattern density is determined, based on a pre-determined target post-PEC maximum dose. The pre-PEC maximum dose is calculated near an edge of the desired shape. Methods also include modifying the original set of exposure information with the pre-PEC maximum dose to create a modified set of exposure information.