Patents by Inventor Akira Ishibashi

Akira Ishibashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6177690
    Abstract: A semiconductor light emitting device having good characteristics, high reliability and long lifetime includes a p-n junction or p-i-n junction made by locating an active layer in a position inside an n-type doped layer or p-type doped layer sufficiently distant from the depletion layer between the p-type doped layer and the n-type doped layer. When a component of intensity of light from the active layer normal to the active layer is P(x), x for its maximum value Pmax is x=0, and the range of x satisfying P(x)>Pmax/e2 is −Ln<x<Lp in a semiconductor light emitting device having a p-n junction, doping concentration of at least a portion of the n-type doped layer where x>−Ln is made lower than doping concentration of the other portion of the n-type doped layer, or doping concentration of at least a part of the p-type doped layer where x<Lp is made lower than doping concentration of the other part of the p-type doped layer.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: January 23, 2001
    Assignee: Sony Corporation
    Inventors: Hiroyasu Noguchi, Eisaku Kato, Akira Ishibashi
  • Patent number: 6031244
    Abstract: A luminescent semiconductor device comprises: an active layer composed of a Group II-VI semiconductor device which comprises at least one Group II element selected from the group consisting of zinc, magnesium, beryllium, cadmium, manganese and mercury, and at least one Group VI element selected from the group consisting of oxygen, sulfur, selenium and tellurium. the Group II-VI compound semiconductor forming said active layer contains at least one element selected from the group consisting of magnesium, beryllium and cadmium as the Group II element and tellurium as the Group VI element. At least one antidiffusion layer preventing diffusion of these elements from the active layer is provided on at least one surface of the active layer.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: February 29, 2000
    Assignee: Sony Corporation
    Inventors: Hiroyasu Noguchi, Kazushi Nakano, Akira Ishibashi, Atsushi Toda, Satoshi Taniguchi, Tomonori Hino, Eisaku Kato
  • Patent number: 5909459
    Abstract: A surface-emitting semiconductor light emitting device comprises an n-type ZnSe buffer layer, n-type ZnSSe layer, n-type ZnMgSSe cladding layer, n-type ZnSSe waveguide layer, active layer, p-type ZnSSe waveguide layer, p-type ZnMgSSe cladding layer, p-type ZnSSe layer,p-type ZnSe contact layer, p-type ZnSe/ZnTe MQW layer and p-type ZnTe contact layer, sequentially stacked on an n-type GaAs substrate. A grid-shaped p-side electrode and a Au film convering the p-side electrode are provided on the p-type ZnTe contact layer. An n-side electrode is provided on the back surface of the n-type GaAs substrate. The active layer has a single quantum well structure or a multiple quantum structure including ZnCdSe quantum well layers.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: June 1, 1999
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Norikazu Nakayama, Satoru Kijima
  • Patent number: 5908306
    Abstract: A semiconductor device exploiting a quantum interference effect is disclosed. The device comprises: a channel region connected multiply with multiplicity of n (n.gtoreq.3) and having (n-1)-fold rotational symmetry around an axis of the channel region; a gate electrode surrounding a side wall of the channel region; and source and drain electrodes electrically connected to one and another end of the channel region along the axis. Electrons move in an effective channel region along or around the axis from the source toward the drain. Electron interference in the effective channel region is controlled by a magnetic field applied in the axis direction and/or the gate electrode.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: June 1, 1999
    Assignees: Sony Corporation, The Board of Trustees of the University of Illinois
    Inventors: Akira Ishibashi, David G. Ravenhall, Roy L. Schult, Henry W. Wyld
  • Patent number: 5898662
    Abstract: A semiconductor light emitting device comprises: a compound semiconductor substrate; an n-type cladding layer on the compound semiconductor substrate; an active layer on the n-type cladding layer; a p-type cladding layer on the active layer: and a p-type contact layer on the p-type cladding layer, the n-type cladding layer, the active layer, the p-type cladding layer and the p-type contact layer being made of II-VI compound semiconductors containing at least one of group II elements selected from the group consisting of Zn, Cd, Mg, Hg and Be and at least one of group VI elements selected from the group consisting of S, Se, Te and O, characterized in that at least the active layer has undulations and at least the p-type layer is flat.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: April 27, 1999
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Satoshi Taniguchi, Tomonori Hino, Takashi Kobayashi, Kazushi Nakano, Norikazu Nakayama
  • Patent number: 5872023
    Abstract: The semiconductor light emitting device includes a semiconductor substrate (1), a first conductivity type first cladding layer (2) deposited on the semiconductor substrate (1), an active layer (4) deposited on the first cladding layer (2), and the second conductivity type second cladding layer (6) deposited on the active layer (4). The first and the second cladding layers (2, 6) are made of the II/VI-compound semiconductors including at least one kind of II group elements such as Zn, Hg, Cd, Mg and at least one kind of VI group elements such as S, Se, Te. The lattice mismatching .DELTA.a/a (%) between at least one of the first cladding layer (2) and the second cladding layer (6) and the substrate is set within the range of -0.9%.ltoreq..DELTA.a/a.ltoreq.0.5% (reference symbols a and a.sub.c represent the lattice constant of the semiconductor substrate and the lattice constant of at least either of the first and second cladding layers, and .DELTA.a is obtained from .DELTA.a=a.sub.c -a).
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: February 16, 1999
    Assignee: Sony Corporation
    Inventors: Masashi Shiraishi, Satoshi Ito, Kazushi Nakano, Akira Ishibashi, Masao Ikeda, Hiroyuki Okuyama, Katsuhiro Akimoto, Tomonori Hino, Masakazu Ukita
  • Patent number: 5828086
    Abstract: A semiconductor light emitting device ccomprises a first cladding layer, an active layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer and the second cladding layer has a superlattice structure comprising II-VI compound semiconductor. Another semiconductor light emitting device comprises a first cladding layer, a first guide layer, an active layer, a second guide layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer, the first guide layer, the second cladding layer and the second guide layer has a superlattice structure. Still anothr semiconductor light emitting device comprises a defect decomposing layer, a defect blocking layer, a first cladding layer, an active layer, a second cladding layer which are stacked on a semiconductor substrate. The defect decomposing layer and the defect blocking layer comprise a superlattice structure.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: October 27, 1998
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Satoshi Matsumoto, Masaharu Nagai, Satoshi Ito, Shigetaka Tomiya, Kazushi Nakano, Etsuo Morita
  • Patent number: 5811831
    Abstract: A semiconductor device exploiting a quantum interference effect is disclosed. The device comprises: a semiconductor body; n-1 (n.gtoreq.3) rods of forbidden regions extending along one direction, the forbidden regions being rotationally asymmetric around the one direction and being changeable in cross sectional area; a channel region consisting of a plurality of elemental channel regions, the forbidden regions dividing the channel region into the plurality of elemental channel regions, each of the elemental channel regions forming a closed circuit and being defined around each of the forbidden regions, the channel region being multiply connected with connectivity of n; and source and drain electrodes electrically connected to one and another ends of the channel region along the one direction.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: September 22, 1998
    Assignee: Sony Corporation
    Inventor: Akira Ishibashi
  • Patent number: 5789600
    Abstract: An electrolytically polymerizable macromolecular compound which is advantageously usable as a surface modifier for a polar surface, as a compatibilizing agent for polymer alloys, as an adhesive primer, as an electrochromic substance, etc., a polymerizable monomer to be used for the production thereof, and a method for the production of an electrolytically polymerized film thereof are disclosed. The macromolecular compound has a repeating unit represented by the following general formula (2): ##STR1## wherein R.sub.1 represents a hydrogen atom or an alkyl group, A represents an electrolytically polymerizable group, and B represents a divalent group.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: August 4, 1998
    Assignee: YKK Corporation
    Inventors: Makoto Sakai, Masaki Wakabayashi, Akira Ishibashi
  • Patent number: 5764672
    Abstract: A semiconductor laser comprises: a first cladding layer of a first conduction type; an active layer stacked on the first cladding layer; and a second cladding layer of a second conduction type stacked on the active layer. The first cladding layer, the active layer and the second cladding layer are made of II-VI compound semiconductors. Pulse oscillation occurs with characteristics of a threshold current I.sub.th (A), a threshold voltage V.sub.th (V) of the diode composed of the first cladding layer, the active layer and the second cladding layer, a differential resistance R.sub.S (.OMEGA.) of the diode after the rising, a thermal resistance R.sub.t (K/W) and a characteristic temperature T.sub.0 (K). When two amounts .alpha. and .beta. are defined by:.alpha..ident.(R.sub.t /T.sub.0)I.sub.th V.sub.th.beta..ident.(R.sub.t /T.sub.0)R.sub.S I.sub.th.sup.2the point (.alpha., .beta.) exists in an area on the .alpha.-.beta. plane surrounded by the straight line .alpha.=0, the straight line .beta.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: June 9, 1998
    Assignee: Sony Corporation
    Inventors: Masakazu Ukita, Akira Ishibashi
  • Patent number: 5740193
    Abstract: A II-VI group compound semiconductor light-emitting device can emit light of a short wavelength at room temperature. Operation characteristics, such as current--voltage characteristics and current--light output characteristics can be stabilized and a life of this semiconductor light-emitting device can be extended. The semiconductor light-emitting device comprises a substrate (1), at least a first cladding layer (2) of a first conductivity type, an active layer (3) and a second cladding layer (4) of a second conductivity type, wherein at least the active layer (3) is made of a II-VI group compound semiconductor and the active layer (3) is doped by either or both of n-type and p-type dopants.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: April 14, 1998
    Assignee: Sony Corporation
    Inventors: Hiroyuki Okuyama, Akira Ishibashi, Eisaku Kato, Hiroshi Yoshida, Kazushi Nakano, Masakazu Ukita, Satoru Kijima, Sakurako Okamoto
  • Patent number: 5732099
    Abstract: A p-type GaAs current block layer is stacked on a (100)-oriented n-type GaAs substrate, and a stripe-shaped groove is formed in the p-type GaAs current block layer to extend in the <01-1> direction. Side surfaces of the groove has the maximum inclination not larger than 60.degree.. The thickness of the p-type GaAs current block layer is 1.5 .mu.m or more. Stacked on the structured substrate having the current narrowed mechanism via an n-type ZnSe buffer layer are an n-type ZnMgSSe cladding layer, n-type ZnSSe waveguide layer, active layer, p-type ZnSSe waveguide layer, p-type ZnMgSSe cladding layer, and others, to establish an index-guided inner-striped semiconductor laser having SCH structure and CSPW structure.
    Type: Grant
    Filed: July 25, 1996
    Date of Patent: March 24, 1998
    Assignee: Sony Corporation
    Inventors: Takayuki Kawasumi, Norikazu Nakayama, Akira Ishibashi, Yoshifumi Mori
  • Patent number: 5665977
    Abstract: A semiconductor light emitting device comprises a first cladding layer, an active layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer and the second cladding layer has a superlattice structure comprising II-VI compound semiconductor. Another semiconductor light emitting device comprises a first cladding layer, a first guide layer, an active layer, a second guide layer and a second cladding layer which are stacked on semiconductor substrate. At least a part of the first cladding layer, the first guide layer, the second cladding layer and the second guide layer has a superlattice structure. Still another semiconductor light emitting device comprises a defect decomposing layer, a defect blocking layer, first cladding layer, an active layer, a second cladding layer which are stacked on a semiconductor substrate. The defect decomposing layer and the defect blocking layer comprise a superlattice structure.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: September 9, 1997
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Satoshi Matsumoto, Masaharu Nagai, Satoshi Ito, Shigetaka Tomiya, Kazushi Nakano, Etsuo Morita
  • Patent number: 5657336
    Abstract: A II-VI group compound semiconductor light-emitting device can emit light of a short wavelength at room temperature. Operation characteristics, such as current--voltage characteristics and current--light output characteristics can be stabilized and a life of this semiconductor light-emitting device can be extended. The semiconductor light-emitting device comprises a substrate (1), at least a first cladding layer (2) of a first conductivity type, an active layer (3) and a second cladding layer (4) of a second conductivity type, wherein at least the active layer (3) is made of a II-VI group compound semiconductor and the active layer (3) is doped by either or both of n-type and p-type dopants.
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: August 12, 1997
    Assignee: Sony Corporation
    Inventors: Hiroyuki Okuyama, Akira Ishibashi, Eisaku Kato, Hiroshi Yoshida, Kazushi Nakano, Masakazu Ukita, Satoru Kijima, Sakurako Okamoto
  • Patent number: 5640409
    Abstract: A semiconductor light-emitting device capable of emitting blue to green light is disclosed. The device comprises a first cladding layer of the first conduction type stacked on a compound semiconductor substrate and made of ZnMgSSe compound semiconductor; an active layer stacked on the first cladding layer; a second cladding layer of the second conduction type stacked on the active layer and made of a ZnMgSSe compound semiconductor; and ZnSSe compound semiconductor layers provided on the second cladding layer and/or between the compound semiconductor substrate and the first cladding layer. The device has good optical confinement characteristics and carrier confinement characteristics, generates only a small amount of heat during its operation, and is fabricated easily.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: June 17, 1997
    Assignee: Sony Corporation
    Inventors: Satoshi Ito, Toyoharu Ohata, Akira Ishibashi, Norikazu Nakayama
  • Patent number: 5635306
    Abstract: The present invention is a honeycomb panel comprising metal face sheets respectively disposed on upper and lower faces of said honeycomb core characterized in that said honeycomb panel has a metal side plate disposed on at least one side face thereof, for mutually connecting honeycomb panels to each other, and a process for producing a honeycomb panel, said process characterized by comprising the steps of: welding a corrugated honeycomb core at an end face of its corrugation to a side plate along the end face of said corrugation; welding the honeycomb core at top portions of its corrugation to an upper face sheet from the side of the honeycomb core by means of an energy beam; welding bottom portions of the corrugation of the honeycomb core to a lower face sheet from the side of the face sheet by means of an energy beam; and welding the face sheets to the side plate before or after welding the honeycomb core to the face sheets.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 3, 1997
    Assignee: Nippon Steel Corporation
    Inventors: Katsuhiro Minamida, Masashi Oikawa, Atsushi Sugihashi, Akira Ishibashi, Mamoru Takeda
  • Patent number: 5633514
    Abstract: The semiconductor light emitting device includes a semiconductor substrate (1), a first conductivity type first cladding layer (2) deposited on the semiconductor substrate (1), an active layer (4) deposited on the first cladding layer (2), and the second conductivity type second cladding layer (6) deposited on the active layer (4). The first and the second cladding layers (2, 6) are made of the II/VI-compound semiconductors including at least one kind of group II elements such as Zn, Hg, Cd, Mg and at least one kind of group VI elements such as S, Se, Te. The lattice mismatching .DELTA.a/a (%) between at least one of the first cladding layer (2) and the second cladding layer (6) and the substrate is set within the range of -0.9%.ltoreq..DELTA.Aa/a.ltoreq.0.5% (reference symbols a and a.sub.c represent the lattice constant of the semiconductor substrate and the lattice constant of at least either of the first and second cladding layers, and .DELTA.a is obtained from .DELTA.a=a.sub.c -a).
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: May 27, 1997
    Assignee: Sony Corporation
    Inventors: Masashi Shiraishi, Satoshi Ito, Kazushi Nakano, Akira Ishibashi, Masao Ikeda, Hiroyuki Okuyama, Katsuhiro Akimoto, Tomonori Hino, Masakazu Ukita
  • Patent number: 5625634
    Abstract: A semiconductor laser comprises: a first cladding layer of a first conduction type; an active layer stacked on the first cladding layer; and a second cladding layer of a second conduction type stacked on the active layer. The first cladding layer, the active layer and the second cladding layer are made of II-VI compound semiconductors. Pulse oscillation occurs with characteristics of a threshold current I.sub.th (A), a threshold voltage V.sub.th (V) of the diode composed of the first cladding layer, the active layer and the second cladding layer, a differential resistance R.sub.S (Q) of the diode after the rising, a thermal resistance R.sub.t (K/W) and a characteristic temperature T.sub.0 (K). When two amounts .alpha. and .beta. are defined by:.alpha..ident.(R.sub.t /T.sub.0)I.sub.th v.sub.th.beta..ident.(R.sub.t /T.sub.0)R.sub.S I.sub.th.sup.2the point (.alpha., .beta.) exists in an area on the .alpha.-.beta. plane surrounded by the straight line .alpha.=0, the straight line .beta.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: April 29, 1997
    Assignee: Sony Corporation
    Inventors: Masakazu Ukita, Akira Ishibashi
  • Patent number: 5617446
    Abstract: A surface-emitting semiconductor light emitting device comprises an n-type ZnSe buffer layer, n-type ZnSSe layer, n-type ZnMgSSe cladding layer, n-type ZnSSe waveguide layer, active layer, p-type ZnSSe waveguide layer, p-type ZnMgSSe cladding layer, p-type ZnSSe layer, p-type ZnSe contact layer, p-type ZnSe/ZnTe MQW layer and p-type ZnTe contact layer, sequentially stacked on an n-type GaAs substrate. A grid-shaped p-side electrode and a Au film convering the p-side electrode are provided on the p-type ZnTe contact layer. An n-side electrode is provided on the back surface of the n-type GaAs substrate. The active layer has a single quantum well structure or a multiple quantum structure including ZnCdSe quantum well layers.
    Type: Grant
    Filed: July 11, 1995
    Date of Patent: April 1, 1997
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Norikazu Nakayama, Satoru Kijima
  • Patent number: 5597740
    Abstract: A light emitting device and a method of fabricating the same in which a first cladding layer is formed on a substrate, then red, green and blue light emitting portions each made of II-VI semiconductor are formed in a horizontal direction with respect to a surface of the substrate on the first cladding layer, then a second cladding layer is formed on the light emitting portions, and the red, green and blue light emitting portions are electrically separated from each other so that three primary color light emitting portions of a self luminous type are formed on the same substrate through single crystal growth process by changing composition of a compound semiconductor layer.
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: January 28, 1997
    Assignee: Sony Corporation
    Inventors: Satoshi Ito, Futoshi Hiei, Akira Ishibashi, Atsushi Toda, Norikazu Nakayama