Abstract: An information processing apparatus includes: a receiver configured to receive an input operation of a user; and a display controller configured to display, in a display area having a first area and a second area, an image. The display controller includes: an icon controller configured to display, in the second area, first icons associated one-to-one with different layouts in splitting the first area, and a first splitter configured to split the first area into split areas based on a layout corresponding to a selected first icon to when the receiver receives an input operation for selecting any of the first icons.

Abstract: A posture adjusting apparatus includes: an ink ejector that has a detachable inkjet head that ejects ink; and a posture adjuster for adjusting a posture of the ink ejector. The ink ejector includes a head fixing member to/from which the inkjet head is attached and detached, and is movable between a first position where an image is formed on a recording medium by the inkjet head and a second position where the inkjet head is attached and detached, and the posture adjuster allows adjustment of an angle of the head fixing member in the second position.

Abstract: A posture adjusting apparatus includes: an ink ejector that has a detachable inkjet head that ejects ink; and a posture adjuster for adjusting a posture of the ink ejector. The ink ejector includes a head fixing member to/from which the inkjet head is attached and detached, and is movable between a first position where an image is formed on a recording medium by the inkjet head and a second position where the inkjet head is attached and detached, and the posture adjuster allows adjustment of an angle of the head fixing member in the second position.

Abstract: A head unit including: an inkjet head that ejects ink; and a fixer to which the inkjet head is fixed, wherein an engaging part is provided to be fixed to one of the inkjet head and the fixer, and an engaged part is provided to be fixed to the other, the inkjet head is fixed to the fixer by engaging the engaging part and the engaged part, and in the engaging part or the engaged part, a rigidity of a portion including one part of an engagement surface on which the engaging part and the engaged part engage with each other is lower than a rigidity of the other portion.

Abstract: A core executing processes in plural threads specifies one gate to read out a state of the gate from a thread progress control unit holding information of plural gates disposed in a loop state, setting a state of a gate disposed subsequently relative to a gate when a state of the gate is set to a first state to a second state, and setting the state of the gate to the first state when a certain period of time elapses from a first request of reading the state for the gate which is set to the second state, by every certain process in each thread. The core executes a next process when the state of the specified gate is the first state, and makes the execution of the next process wait until the state becomes the first state when it is not the first state.

Abstract: A node includes a sending unit that sends a signal to another node; a receiving unit that receives a signal from another node; a determining unit that determines, when the sending unit sends a signal to the other node, that synchronization has been established with the other node, that determines, when the receiving unit receives a signal from another node, that synchronization has been established with the other node, and that determines, when a node in which synchronization has already been established with the other two nodes in each of which synchronization has been established, that synchronization has been established with the nodes; and a selecting unit that selects an information processing apparatus that is not determined, by the determining unit, that synchronization has been established as the other node at the sending destination for the signal.

Abstract: The present invention includes a plurality of computing units executing a plurality of threads including a communication control thread to which a receiving process by polling is assigned. In a CPU core, a computing unit executing the communication control thread performs polling in a memory region indicating notification of arrival of data and waits for execution of the receiving process until arrival of data, and when a computing unit executing an application thread executes a process assigned to the application thread, the computing unit executing the communication control thread moves to a resource-saving mode in which the use of physical resources is suppressed.

Abstract: An information processing apparatus 1 includes a memory 13 that stores information used for arithmetic processing. The information processing apparatus 1 includes a CPU 11 that operates arithmetic processing by using the information stored in the memory 13. The information processing apparatus 1 includes a measuring unit 15 that measures power consumption of the memory 13. The information processing apparatus 1 includes a CPU frequency controlling unit setting unit 31 that sets an operating frequency of the CPU 11 according to the power consumption measured by the measuring unit 15.

Abstract: An information processing apparatus 1 includes a memory 13 that stores information used for arithmetic processing. The information processing apparatus 1 includes a CPU 11 that operates arithmetic processing by using the information stored in the memory 13. The information processing apparatus 1 includes a measuring unit 15 that measures power consumption of the memory 13. The information processing apparatus 1 includes a CPU frequency controlling unit setting unit 31 that sets an operating frequency of the CPU 11 according to the power consumption measured by the measuring unit 15.

Abstract: A port number is stored in a memory in association with one or more addresses using a data block by which at least one port number associated with a predetermined number of consecutive addresses is written into the memory. Further, a first port number assigned to output ports each being provided for different one of a plurality of relay nodes is stored in association with first consecutive addresses in such a manner that one or more data blocks including the first port number associated with the first consecutive addresses are written into the memory.

Abstract: A core executing processes in plural threads specifies one gate to read out a state of the gate from a thread progress control unit holding information of plural gates disposed in a loop state, setting a state of a gate disposed subsequently relative to a gate when a state of the gate is set to a first state to a second state, and setting the state of the gate to the first state when a certain period of time elapses from a first request of reading the state for the gate which is set to the second state, by every certain process in each thread. The core executes a next process when the state of the specified gate is the first state, and makes the execution of the next process wait until the state becomes the first state when it is not the first state.

Abstract: A node includes a sending unit that sends a signal to another node; a receiving unit that receives a signal from another node; a determining unit that determines, when the sending unit sends a signal to the other node, that synchronization has been established with the other node, that determines, when the receiving unit receives a signal from another node, that synchronization has been established with the other node, and that determines, when a node in which synchronization has already been established with the other two nodes in each of which synchronization has been established, that synchronization has been established with the nodes; and a selecting unit that selects an information processing apparatus that is not determined, by the determining unit, that synchronization has been established as the other node at the sending destination for the signal.

Abstract: An image forming apparatus includes a buffer configured to temporarily store in the buffer toner supplied from a toner cartridge and to be fed to a developing unit; a magnetic reed switch configured to sense magnet variation occurring in a sensing range and sequentially output signals each indicating a result of the sensing; a toner level indicator plate disposed within the buffer to swing up and down about a fixed edge in response to a change in a level of the toner that remains in the buffer, the toner level indicator plate having a magnet on a free edge thereof, the magnet being made to reach the sensing range in a state where the toner level indicator plate has swung down.

Abstract: A prohibition turn determination apparatus determines an initial path so that the communication amounts of respective links connecting switches to each other are most efficiently distributed between a communication pair, that is, a pair of servers communicating with each other via a network. Then, the prohibition turn determination apparatus calculates the communication amounts of respective turns formed along the initial path based on the communication amounts set between end nodes which are the communication pair. Next, the prohibition turn determination apparatus determines prohibition turns, which are not used for packet communication, based on the communication amounts of respective turns by an Up/down method or a TP method. Finally, the prohibition turn determination apparatus determines the final routing to avoid the prohibition turns.

Abstract: A computer acquires correspondence data including a plurality of combinations of identifiers of selected computers, in which parallel processes are started, and identifiers of the parallel processes, wherein the selected computers are among a plurality of computers connected to a multipath network having relay devices extending over two or more hierarchies. The computer specifies a network identifier to be used for distributing communication paths among the selected computers for every selected computer that includes an identifier in the correspondence data, wherein the specified network identifiers is among network identifiers of respective communication paths in the multipath network, and the specified network identifier corresponds to each identifier of a plurality of computers, and is used for routing.

Abstract: The present invention includes a plurality of computing units executing a plurality of threads including a communication control thread to which a receiving process by polling is assigned. In a CPU core, a computing unit executing the communication control thread performs polling in a memory region indicating notification of arrival of data and waits for execution of the receiving process until arrival of data, and when a computing unit executing an application thread executes a process assigned to the application thread, the computing unit executing the communication control thread moves to a resource-saving mode in which the use of physical resources is suppressed.

Abstract: An initial address allocating unit 11 allocates a predetermined address to each of the nodes 21 connected to respective first stage switches 22. A connecting state acquiring unit 12 acquires a connecting state from each of the first stage switches 22, each of second stage switches 23 and each of third stage switches 24. An erroneous connection detecting unit 13 compares the connecting state acquired by the connecting state acquiring unit 12 with a prestored predetermined connecting state, thereby detecting an erroneous connection. An address changing unit 14 changes an address of the node 21 allocated by the initial address allocating unit 11 to satisfy a first predetermined condition based on the connecting state, when the erroneous connection is detected by the erroneous connection detecting unit 13.

Abstract: First-stage switches (B1 to B9), second-stage switches (M1 to M9), and third-stage switches (T1 to T9) include a bottom connection path that configure to interchange a connection point of one or more second signal transmitting units and a connection point of another one or more second signal transmitting units, in a Fat Tree configuration between the first-stage switches (B1 to B9) and the second-stage switches (M1 to M9) constituting a one-set Fat Tree with the third-stage switches (T1 to T9).

Abstract: In response to an all-to-all inter-process communication request from a local process, a computer repeatedly determines a destination server in accordance with a destination-server determination procedure so that, in a same round of destination-server determinations repeatedly performed by the respective servers during all-to-all inter-process communication, the servers determine servers that are different from one another as destination servers. Each time the destination server is determined, the computer sequentially determines a process running on the determined destination server as a destination process.

Abstract: A processor has a first table including an entry that associates a logical address with a physical address of a page that manages a virtual space address. The processor determines, when a target logical address accessed by one of threads is translated to the physical address, whether an entry corresponding to the target logical address is present in the first table, the target logical address is of a page accessed by a program. The processor determines, when the entry corresponding to the target logical address is not present in the first table, whether the target logical address has been accessed during the running of the program. The processor delays, when the target logical address has not yet been accessed, the process of reading the entry corresponding to the target logical address from a page table into the first table by a predetermined time to thereby delay the one thread.