Abstract: This method includes: obtaining first data including identifiers of selected computers for invocation of parallel processes among plural computers connected to lowest-layer relay apparatuses in a network including relay apparatuses in plural layers, wherein the network includes paths between a relay apparatus in a first layer and plural relay apparatuses in a second layer that is an immediately upper layer than the first layer; and selecting, for each of the selected computers and from network identifiers for respective communication routes, network identifiers to be used for communication with other selected computers so as to avoid coincidence of communication routes between the selected computers for which a same difference value is calculated between identification numbers, wherein the network identifiers are associated in advance with an identifier of each of the plural computers and are used for routing in the network, and the identification numbers are assigned for ordering the selected computers.

Abstract: An image formation apparatus including: a toner cartridge storing toner; a developer; a hopper temporarily storing toner supplied from the toner cartridge and supplying the developer with the toner; a magnetic sensor including a magnet and a reed switch that determines whether the magnet is within a detection area thereof, one of which is fixed to a predetermined position, and the other of which is configured to move downwards as a surface level of toner stored in a toner storage of the hopper decreases and thus serves as a surface level detector for detecting the surface level; a lifter configured to periodically lift the surface level detector above the surface level such that the magnet goes out of the detection area; and an ON-edge detector configured to detect ON-edges each indicating a point in time when the magnet has entered the detection area.

Abstract: An information processing apparatus includes a plurality core sections, an uncore section, and a scheduler. The plurality of core sections correspond to processor cores in a multi-core processor. The uncore section is a resource shared by the core sections. The scheduler controls execution timing for a first process so as to make an unused core section execute the first process in a period in which a second process other than the first process is executed by a part of the plurality of core sections. Controlling the execution timing for the first process is permitted.

Abstract: First-stage switches (B1 to B9), second-stage switches (M1 to M9), and third-stage switches (T1 to T9) include a bottom connection path that configure to interchange a connection point of one or more second signal transmitting units and a connection point of another one or more second signal transmitting units, in a Fat Tree configuration between the first-stage switches (B1 to B9) and the second-stage switches (M1 to M9) constituting a one-set Fat Tree with the third-stage switches (T1 to T9).

Abstract: An initial address allocating unit 11 allocates a predetermined address to each of the nodes 21 connected to respective first stage switches 22. A connecting state acquiring unit 12 acquires a connecting state from each of the first stage switches 22, each of second stage switches 23 and each of third stage switches 24. An erroneous connection detecting unit 13 compares the connecting state acquired by the connecting state acquiring unit 12 with a prestored predetermined connecting state, thereby detecting an erroneous connection. An address changing unit 14 changes an address of the node 21 allocated by the initial address allocating unit 11 to satisfy a first predetermined condition based on the connecting state, when the erroneous connection is detected by the erroneous connection detecting unit 13.

Abstract: An information processing apparatus 1 includes a memory 13 that stores information used for arithmetic processing. The information processing apparatus 1 includes a CPU 11 that operates arithmetic processing by using the information stored in the memory 13. The information processing apparatus 1 includes a measuring unit 15 that measures power consumption of the memory 13. The information processing apparatus 1 includes a CPU frequency controlling unit setting unit 31 that sets an operating frequency of the CPU 11 according to the power consumption measured by the measuring unit 15.

Abstract: An instruction trace of a first instruction string is generated from a second instruction string obtained by sampling, at predetermined intervals, the first instruction string. The second instruction string is divided into partial instruction strings. A combination of the partial instruction strings is selected based on the similarity of stored partial instruction strings. A plurality of combination patterns are generated by combining instructions included in the selected partial instruction strings. A likelihood is calculated for each of the combination patterns, and the combination patterns are stored in the storage unit based on the likelihood.

Abstract: A port number is stored in a memory in association with one or more addresses using a data block by which at least one port number associated with a predetermined number of consecutive addresses is written into the memory. Further, a first port number assigned to output ports each being provided for different one of a plurality of relay nodes is stored in association with first consecutive addresses in such a manner that one or more data blocks including the first port number associated with the first consecutive addresses are written into the memory.

Abstract: This method includes: obtaining first data including identifiers of selected computers for invocation of parallel processes among plural computers connected to lowest-layer relay apparatuses in a network including relay apparatuses in plural layers, wherein the network includes paths between a relay apparatus in a first layer and plural relay apparatuses in a second layer that is an immediately upper layer than the first layer; and selecting, for each of the selected computers and from network identifiers for respective communication routes, network identifiers to be used for communication with other selected computers so as to avoid coincidence of communication routes between the selected computers for which a same difference value is calculated between identification numbers, wherein the network identifiers are associated in advance with an identifier of each of the plural computers and are used for routing in the network, and the identification numbers are assigned for ordering the selected computers.

Abstract: An apparatus for controlling devices for searching homology of queries in a base sequence in parallel, includes: a memory for storing a base sequence and an appearing frequency of each of first strings each having a fixed length appearing in the base sequence; and a processor for executing a process including: obtaining queries for searching homology in the base sequence; retrieving each of second strings each having a longer fixed length then that of first strings and partially appearing in each of the queries; determining an approximate appearing frequency of each of the second string on the basis of the appearing frequency of the first strings; evaluating for each of the query sequences a load of task for searching homology; and allocating each task for searching homology for each of the queries among the devices on the basis of the result of evaluation of the load of the each task.

Abstract: A prohibition turn determination apparatus determines an initial path so that the communication amounts of respective links connecting switches to each other are most efficiently distributed between a communication pair, that is, a pair of servers communicating with each other via a network. Then, the prohibition turn determination apparatus calculates the communication amounts of respective turns formed along the initial path based on the communication amounts set between end nodes which are the communication pair. Next, the prohibition turn determination apparatus determines prohibition turns, which are not used for packet communication, based on the communication amounts of respective turns by an Up/down method or a TP method. Finally, the prohibition turn determination apparatus determines the final routing to avoid the prohibition turns.

Abstract: A computer acquires correspondence data including a plurality of combinations of identifiers of selected computers, in which parallel processes are started, and identifiers of the parallel processes, wherein the selected computers are among a plurality of computers connected to a multipath network having relay devices extending over two or more hierarchies. The computer specifies a network identifier to be used for distributing communication paths among the selected computers for every selected computer that includes an identifier in the correspondence data, wherein the specified network identifiers is among network identifiers of respective communication paths in the multipath network, and the specified network identifier corresponds to each identifier of a plurality of computers, and is used for routing.

Abstract: An image formation apparatus including: a toner cartridge storing toner; a developer; a hopper temporarily storing toner supplied from the toner cartridge and supplying the developer with the toner; a magnetic sensor including a magnet and a reed switch that determines whether the magnet is within a detection area thereof, one of which is fixed to a predetermined position, and the other of which is configured to move downwards as a surface level of toner stored in a toner storage of the hopper decreases and thus serves as a surface level detector for detecting the surface level; a lifter configured to periodically lift the surface level detector above the surface level such that the magnet goes out of the detection area; and an ON-edge detector configured to detect ON-edges each indicating a point in time when the magnet has entered the detection area.

Abstract: Provided is an image forming apparatus that includes: a buffer configured to temporarily store therein toner supplied from a toner cartridge and to be fed to a developing unit; a magnetic reed switch configured to sense magnet variation occurring in a sensing range and sequentially output signals each indicating a result of the sensing; a toner level indicator plate disposed within the buffer to swing up and down about a fixed edge in response to a change in a level of the toner that remains in the buffer, the toner level indicator plate having a magnet on a free edge thereof, the magnet being made to reach the sensing range in a state where the toner level indicator plate has swung down.

Abstract: A recovery port, through which waste powder is recovered, is formed at one end of a waste powder recovery container. A conveying member for conveying the waste powder, which has been recovered through the recovery port, from one end to the other end is disposed inside the waste powder recovery container. The conveying member includes a first conveying portion positioned on a side of the recovery port, for conveying the waste powder to the other end, and a second conveying portion for dispersing in a widthwise direction the waste powder conveyed by the first conveying portion.

Abstract: In response to an all-to-all inter-process communication request from a local process, a computer repeatedly determines a destination server in accordance with a destination-server determination procedure so that, in a same round of destination-server determinations repeatedly performed by the respective servers during all-to-all inter-process communication, the servers determine servers that are different from one another as destination servers. Each time the destination server is determined, the computer sequentially determines a process running on the determined destination server as a destination process.

Abstract: A processor has a first table including an entry that associates a logical address with a physical address of a page that manages a virtual space address. The processor determines, when a target logical address accessed by one of threads is translated to the physical address, whether an entry corresponding to the target logical address is present in the first table, the target logical address is of a page accessed by a program. The processor determines, when the entry corresponding to the target logical address is not present in the first table, whether the target logical address has been accessed during the running of the program. The processor delays, when the target logical address has not yet been accessed, the process of reading the entry corresponding to the target logical address from a page table into the first table by a predetermined time to thereby delay the one thread.

Abstract: A recovery port, through which waste powder is recovered, is formed at one end of a waste powder recovery container. A conveying member for conveying the waste powder, which has been recovered through the recovery port, from one end to the other end is disposed inside the waste powder recovery container. The conveying member includes a first conveying portion positioned on a side of the recovery port, for conveying the waste powder to the other end, and a second conveying portion for dispersing in a widthwise direction the waste powder conveyed by the first conveying portion.

Abstract: An apparatus for controlling devices for searching homology of queries in a base sequence in parallel, includes: a memory for storing a base sequence and an appearing frequency of each of first strings each having a fixed length appearing in the base sequence; and a processor for executing a process including: obtaining queries for searching homology in the base sequence; retrieving each of second strings each having a longer fixed length then that of first strings and partially appearing in each of the queries; determining an approximate appearing frequency of each of the second string on the basis of the appearing frequency of the first strings; evaluating for each of the query sequences a load of task for searching homology; and allocating each task for searching homology for each of the queries among the devices on the basis of the result of evaluation of the load of the each task.

Abstract: An instruction-trace generating device generates an instruction trace of a first instruction string from a second instruction string obtained by sampling, at predetermined intervals, the first instruction string executed a plurality of times.