Patents by Inventor Akira Yajima

Akira Yajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6624504
    Abstract: A semiconductor apparatus includes a semiconductor device having circuit electrodes aligned centrally of the semiconductor apparatus. A first electrically insulating layer is formed on said semiconductor device with said circuit electrodes being exposed from said first insulating layer. A second electrically insulating layer is formed on said first insulating layer, and external connection terminals are formed on said second insulating layer. A wiring is formed on said second insulating layer to electrically connect said external connect terminals to said circuit electrodes of said semiconductor device, and a third electrically insulating layer is formed on said second insulating layer and on said wiring. Particles are provided in the second insulating layer to control a shape of said second insulating layer.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: September 23, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
  • Publication number: 20030153172
    Abstract: The corrosion of a pad portion on TEG is prevented, and the wettability of a solder and the shear strength after solder formation of a pad portion of an actual device are improved. A third layer wiring M3 on a chip area CA of a semiconductor wafer and a third layer wiring M3 on a scribe area SA are respectively comprised of a TiN film M3a, an Al alloy film M3b, and a TiN film M3c. A second pad portion PAD2 as the top of a rewiring 49 on the chip area CA is cleaned. Alternatively, an Au film 53a is formed thereon by an electroles splating method. Further, after the formation of the Au film 53a, a retention test is carried out. Thereafter, further, an Au film 53b is formed and a solder bump electrode 55 is formed. As a result, it is possible to prevent the corrosion of a first pad portion PAD1 of the third layer wiring M3 on the scribe area SA which is TEG due to a plating solution or the like by the TiN film M3c.
    Type: Application
    Filed: January 14, 2003
    Publication date: August 14, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Akira Yajima, Kenichi Yamamoto, Hiromi Abe
  • Publication number: 20020063332
    Abstract: The object of the present invention is to realize a semiconductor device enabling a flip chip connection without use of underfill.
    Type: Application
    Filed: March 20, 2001
    Publication date: May 30, 2002
    Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Kosuke Inoue, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Naoya Kanda, Madoka Minagawa, Ichiro Anjo, Asao Nishimura, Kenji Ujiie, Akira Yajima
  • Patent number: D289617
    Type: Grant
    Filed: June 6, 1984
    Date of Patent: May 5, 1987
    Assignee: Shiojiri Kogyo Kabushiki Kaisha
    Inventor: Akira Yajima
  • Patent number: D330169
    Type: Grant
    Filed: March 13, 1990
    Date of Patent: October 13, 1992
    Assignee: Seiko Epson Corporation
    Inventor: Akira Yajima