Patents by Inventor Akira Yamazaki

Akira Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device, method of fabricating the same and semiconductor device fabricating apparatus
    Patent number: 6784021
    Abstract: In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: August 31, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shunichi Abe, Tetsuya Uebayashi, Naoki Izumi, Akira Yamazaki
  • Pseudo-static synchronous semiconductor memory device
    Publication number: 20040165472
    Abstract: For a pseudo-SRAM (Static Random Access Memory) macro operating in synchronization with a clock signal, a page operation instructing signal instructing a page operation and a page close instructing signal instructing completion of the page operation are prepared as control signals designating operation modes. A pseudo-SRAM can be selectively operated in a page mode in accordance with the page operation instructing signal and the page close instructing signal, and an operation of row-related circuitry in each clock cycle can be inhibited so that an average power consumption can be reduced. The power consumption of the pseudo-SRAM can be reduced without lowering an operation speed.
    Type: Application
    Filed: September 26, 2003
    Publication date: August 26, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Akira Yamazaki
  • Clock generating circuit
    Patent number: 6781431
    Abstract: The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: August 24, 2004
    Assignees: Rensas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventors: Yasuhiko Taito, Akira Yamazaki, Fukashi Morishita, Nobuyuki Fujii, Mihoko Akiyama, Mako Okamoto
  • Semiconductor memory device with power consumption reduced in non-data-access
    Patent number: 6781903
    Abstract: A semiconductor memory device includes a first data line electrically connected to selected one of a plurality of memory cells in response to activation of a word line, a second data line provided hierarchically with respect to the first data line, a read circuit provided between the first data line and the second data line to drive the second data line to a fixed voltage with a driving power according to a voltage on the first data line at the time of data reading, and a voltage supply control circuit for supplying a predetermined voltage to the second data line in response to a precharge/equalize instruction. The voltage supply control circuit includes a voltage supply stop circuit disconnecting the second data line from the predetermined voltage in a predetermined period except for the time of data reading.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: August 24, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Atsuo Mangyo, Masaru Haraguchi, Akira Yamazaki
  • Semiconductor integrated circuit with voltage down converter adaptable for burn-in testing
    Patent number: 6777707
    Abstract: A VDC circuit that supplies an internal voltage VDD1 to an internal circuit in a normal operation forces a transistor off in a burn-in test mode through input of a test signal to suppress supply of an external power supply voltage VDDH to a node. In a burn-in test mode, an external power supply voltage lower than external power supply voltage VDDH and higher than internal voltage VDD1 is supplied from an external pad.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: August 17, 2004
    Assignees: Renesas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventors: Mihoko Akiyama, Akira Yamazaki, Fukashi Morishita, Yasuhiko Taito, Nobuyuki Fujii, Mako Okamoto
  • Multi-power semiconductor integrated circuit device
    Patent number: 6768354
    Abstract: With power-on detection circuits provided for a plurality of power supply voltages, a main power-on detection signal is maintained at the active state to reset an internal node while at least one of the power-on detection signals is active. In a multi-power semiconductor integrated circuit device, current consumption at the time of power-up is reduced.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: July 27, 2004
    Assignees: Renesas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventors: Akira Yamazaki, Fukashi Morishita, Yasuhiko Taito, Nobuyuki Fujii, Mihoko Akiyama, Mako Kobayashi
  • Semiconductor device
    Patent number: 6737736
    Abstract: A semiconductor device and a manufacturing method for downsizing and densification achieved by reducing the thickness of the semiconductor device without an increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed overlapping in height the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, wires connect the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wires. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: May 18, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shunichi Abe, Tetsuya Uebayashi, Naoki Izumi, Akira Yamazaki
  • Semiconductor memory device with power consumption reduced in non-data-access
    Publication number: 20040081009
    Abstract: A semiconductor memory device includes a first data line electrically connected to selected one of a plurality of memory cells in response to activation of a word line, a second data line provided hierarchically with respect to the first data line, a read circuit provided between the first data line and the second data line to drive the second data line to a fixed voltage with a driving power according to a voltage on the first data line at the time of data reading, and a voltage supply control circuit for supplying a predetermined voltage to the second data line in response to a precharge/equalize instruction. The voltage supply control circuit includes a voltage supply stop circuit disconnecting the second data line from the predetermined voltage in a predetermined period except for the time of data reading.
    Type: Application
    Filed: April 9, 2003
    Publication date: April 29, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Atsuo Mangyo, Masaru Haraguchi, Akira Yamazaki
  • Substrate bias voltage generating circuit
    Patent number: 6700434
    Abstract: Oscillation outputs which are different for respective detector signals output from a first detector circuit and a second detector circuit, are obtained from a first ring oscillator and a second ring oscillator respectively corresponding to the detector circuits. A selector selects and outputs one of the oscillation outputs. Accordingly, it is sufficient to provide only one pump circuit in a circuit producing a substrate bias voltage.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: March 2, 2004
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.
    Inventors: Nobuyuki Fujii, Fukashi Morishita, Mihoko Akiyama, Akira Yamazaki, Mako Kobayashi, Yasuhiko Taito
  • Semiconductor circuit device capable of accurately testing embedded memory
    Publication number: 20040013016
    Abstract: A test clock signal for determining a timing of transferring a signal to an embedded memory, a memory clock signal for determining a timing of latching a signal/data of the embedded memory, and a latch timing signal for sampling a signal read from the memory are selectively sampled in accordance with a correcting test clock signal by a common flip flop. The phase differences of the latch timing signal, test clock signal and memory clock signal are measured externally. Thus, it is possible to accurately measure timing conditions such as set up/hold time and access time of the embedded synchronous memory.
    Type: Application
    Filed: March 7, 2003
    Publication date: January 22, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Yamazaki, Atsuo Mangyo
  • Semiconductor memory device including internal power circuit having tuning function
    Patent number: 6665217
    Abstract: A tuning control circuit includes fuse devices each shifting from a conductive state to an interrupted state in response to a program input from the outside, and signal driving circuits for driving the signal levels of tuning control signals in accordance with the states of the fuse devices. A reference voltage generating circuit generates a reference voltage corresponding to a reference value of a memory array voltage of a semiconductor memory device according to the invention in accordance with an electrical resistance value which is finely adjusted in response to the tuning control signals.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: December 16, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fukashi Morishita, Yasuhiko Taito, Akira Yamazaki, Mako Okamoto, Nobuyuki Fujii
  • Semiconductor integrated circuit device having data input/output configuration variable
    Publication number: 20030214845
    Abstract: In an embedded DRAM core of which word configuration can be varied, a modifying circuit selects either word configuration designating information from a metal word configuration setting circuit setting the word configuration with metal slice or word configuration designating information stored in a register, and supplies the selected information to an I/O switch. The I/O switch sets an internal switch gate to a conductive or non-conductive state in accordance with the received word configuration information, and electrically sets a connection path of a preamplifier/write driver and a DQ buffer. A test can be performed while operating an embedded DRAM macro under an actual use condition.
    Type: Application
    Filed: February 20, 2003
    Publication date: November 20, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Akira Yamazaki
  • Potential detecting circuit having wide operating margin and semiconductor device including the same
    Patent number: 6614270
    Abstract: In a detector included in a VPP generating circuit in a DRAM, an external power supply potential is applied to the gate of an N-channel MOS transistor for regulating a through current of an inverter for outputting an inversion signal of an output signal of a comparator. Since a drain-source voltage of the N-channel MOS transistor can be set to be lower than a threshold voltage Vthn of the N-channel MOS transistor, an operation margin of the detector under conditions of a low voltage and a low temperature is made wider as compared with a conventional technique.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: September 2, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company Limited
    Inventors: Mako Okamoto, Yasuhiko Taito, Fukashi Morishita, Akira Yamazaki, Mihoko Akiyama, Nobuyuki Fujii
  • Semiconductor device provided with potential transmission line
    Patent number: 6593642
    Abstract: A DRAM is provided at a portion relating to generation of a boosted potential with a filter circuit located between a detector circuit and a ring oscillator for removing a pulse-like change in level from an output signal of the detector circuit. Accordingly, temporary stop of the charge pump circuit can be prevented even when the boosted potential exceeds in a pulse-like manner the reference potential at the vicinity of the output node of the charge pump circuit, and the boosted potential can be rapidly restored to the reference potential.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: July 15, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mako Okamoto, Yasuhiko Taito, Fukashi Morishita, Akira Yamazaki, Nobuyuki Fujii
  • Clock generating circuit
    Publication number: 20030117204
    Abstract: The clock generating circuit includes: an oscillator generating a reference clock signal; an EX-OR gate connected in a ring configuration; and first and second D latch circuits. The EX-OR gate inverts a clock signal to provide the inverted clock signal to the first D latch circuit when an activating signal is at H level. In this case, the clock signal is a clock signal having a clock cycle period of twice that of the reference clock signal. The EX-OR gate provides the clock signal direct to the first D latch circuit when the activating signal is set to L level. In this case, level transition of the clock signal is ceased. Hence, generation of a glitch in the clock signal is prevented from occurring.
    Type: Application
    Filed: January 23, 2003
    Publication date: June 26, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yasuhiko Taito, Akira Yamazaki, Fukashi Morishita, Nobuyuki Fujii, Mihoko Akiyama, Mako Okamoto
  • Semiconductor integrated circuit device
    Publication number: 20030116763
    Abstract: A comparator compares a predetermined number of data bits with respective expected value data bits. A select circuit selects either of an output signal of this comparator and the predetermined number of data bits in accordance with an operation mode instructing signal for transference to test output nodes. A test of a logic merged memory is executed continuously to a space column space and a normal column space of the memory.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 26, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Akira Yamazaki, Takeshi Fujino, Atsuo Mangyo
  • Lead frame
    Publication number: 20030062604
    Abstract: A section of predetermined geometry and area is provided on or in a die pad of a lead frame and taken as a mark to be used for checking the position of a semiconductor chip. If the semiconductor chip is placed outside an allowable range in the X direction, the semiconductor chip overlaps the mark, thereby changing the geometry of an observable portion (slanted portion) of the mark. By means of the change, a positional deviation of the semiconductor chip in the X direction can be ascertained. A positional deviation of the semiconductor chip in Y direction is determined, by observing whether or not an electrode is situated between extensions of sides of a certain portion of the section.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 3, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tetsuya Uebayashi, Shunichi Abe, Naoki Izumi, Akira Yamazaki
  • Semiconductor device, method of producing the same and semiconductor production equipment for carrying out the method
    Publication number: 20030059981
    Abstract: A semiconductor chip mounting substrate provided with an adhesive layer is placed on a first supporting device included in a chip bonding unit. A collet holds a semiconductor chip, carries the same to the semiconductor chip mounting substrate placed on the first supporting device and presses the same against the semiconductor chip mounting substrate to bond the semiconductor chip temporarily to the semiconductor chip mounting substrate. The semiconductor chip mounting substrate to which the semiconductor chip is bonded temporarily is placed on a second supporting device included in a chip pressing unit. A pressing device applies pressure to the semiconductor chip to straighten the warped semiconductor chip and to bond the same entirely to the semiconductor chip mounting substrate.
    Type: Application
    Filed: June 3, 2002
    Publication date: March 27, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shunichi Abe, Tetsuya Uebayashi, Naoki Izumi, Akira Yamazaki
  • Semiconductor device, and method of manufacturing the semiconductor device
    Publication number: 20030054591
    Abstract: The semiconductor device is manufactured as follows. That is, after the die pad section, on which the semiconductor chip is mounted, the inner lead section and at least a part of the outer lead section are arranged in the cavity of the metal mold on the lead frame. Moreover, the sealing resin is filled into the cavity of the metal mold and hardened therein. Moreover, the sealing resin located on a surface layer region of the outer lead section of the lead frame removed.
    Type: Application
    Filed: March 6, 2002
    Publication date: March 20, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shunichi Abe, Tetsuya Uebayashi, Naoki Izumi, Akira Yamazaki
  • Semiconductor device, method of fabricating the same and semiconductor device fabricating apparatus
    Publication number: 20030049915
    Abstract: In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.
    Type: Application
    Filed: March 6, 2002
    Publication date: March 13, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shunichi Abe, Tetsuya Uebayashi, Naoki Izumi, Akira Yamazaki