Abstract: A semiconductor integrated circuit device includes an SDRAM module operating in synchronization with a clock signal, a logic circuit transmitting data with the SDRAM module for effecting necessary processing, a direct memory access circuit taking in and transferring an externally applied signal in synchronization with the clock signal corresponding to an operation clock of the SDRAM module, and a selector selecting either the output signal of the logic circuit and the output signal of the direct memory access circuit in accordance with a test mode instructing signal for application to the SDRAM module. A test of a synchronous memory can be performed by externally making fast and direct access to the synchronous memory without an influence of a skew in a signal.

Abstract: A memory includes a built-in testing circuit for determining pass/fail of a memory portion and an identifier register for storing identification value for identifying the memory. The memory performs a testing operation according to a command provided from a controller via a send link and sends the result of that testing to a sync link. Thus, the memory controller can identify a defective memory cell. In this way, erroneous operation of the system due to a defective memory cell in a memory system can be prevented.

Abstract: A video telephone (1) includes a communication block (2) having a telephone communication function and a display block (3) assembled so as to be mounted on the communication block (2) and having a television function. The display block (3) includes a display screen (4) and a television camera. The display block (3) can be adjusted in tilt with respect to the communication block (2).

Abstract: A dynamic random access memory DRAM includes banks which are driven to active or inactive states independently of each other. Activation/inactivation of these banks are controlled by row controllers operating independently of each other, whereby a page or word line can be selected in each of the banks, a page hit rate can be increased, and the number of array precharge operation times in a page error as well as power consumption can be reduced in response. Thus, the cache hit rate of a processor having a built-in DRAM is increased and power consumption is reduced.

Abstract: Columns included in a sub-block are divided into first and second groups. If a defective memory cell column is present in the first group, an address comparison circuit activates a signal to select a redundant memory cell column, then selection prohibiting signal attains an "L" level based on information programmed in a programming circuit, a selection of a column in the first group is prohibited, and a redundant memory cell column selection signal is activated. Meanwhile, a normal selecting operation is performed to the second column group.

Abstract: A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector, and are provided to the core unit of the synchronous dynamic random access memory for testing.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.

Abstract: A dynamic random access memory DRAM includes banks which are driven to active or inactive states independently of each other. Activation/inactivation of these banks are controlled by row controllers operating independently of each other, whereby a page or word line can be selected in each of the banks, a page hit rate can be increased, and the number of array precharge operation times in a page error as well as power consumption can be reduced in response. Thus, the cache hit rate of a processor having a built-in DRAM is increased and power consumption is reduced.

Abstract: A memory includes a counter by an operation mode designating command for counting a clock signal, and a circuit for generating an internal operation timing control signal according to the count value of the counter. Activation/inactivation of an internal operation control signal is done in synchronization with a clock signal. It is not necessary to take into consideration the margin with respect to an internal operation control signal. High speed operation can be carried out stably. By providing a signal indicating an internal operation state according to the count value of the counter, the load of an external memory controller for monitoring a command issue timing can be reduced. A high speed operating memory is provided that can reduce the load of a memory controller and that can set the internal operation timing accurately.

Abstract: A television reception controller enables the viewer to choose a favorite program from among many broadcasting channels easily and swiftly. The controller displays labels of categories that are NEWS, MOVIE, SPORTS, POLITICS and MUSIC on the top row of the display screen and displays pictures of broadcasting channels of the leftmost category, which have been received in the last four weeks, in small frames in the leftmost column of the screen downwardly in the order of the frequency of reception. The controller responds to the horizontal movement of the cursor to rotate the category labels horizontally and responds to the vertical movement of the cursor on the small-frame pictures and the action of selection to display the picture of the selected broadcasting channel in the main frame of the screen.

Abstract: A semiconductor memory device includes a DRAM array and an SRAM array, a write data transfer buffer for storing data from the SRAM array to the DRAM array, and a read data transfer buffer for storing data from the SRAM array to the DRAM array. These DTBR and DTBW can be accessed via an input/output buffer. The semiconductor memory device further includes a graphic data readout buffer storing only graphic data. This graphic data readout buffer provides the stored data outside the memory device via the input/output buffer, and also receives and stores graphic data from the DRAM array via the DTBR. A cache for graphic data of an optimum size can be implanted. A multimedia application specific memory device can be provided which implements an efficient graphic data cache and a high hit rate CPU cache.

Abstract: A television signal receiver equipped with a picture display controller and adapted for selecting a desired program quickly from a multiplicity of broadcast programs. In response to designation of a browsing mode, many subsidiary pictures are displayed successively under a main picture in a manner to be scrollable in any of predetermined directions. When a desired subsidiary picture is displayed within a cursor, the program being displayed on the relevant subsidiary screen is registered in a bookmark list by actuating a bookmark button switch incorporated in a remote commander. A bookmark is additionally displayed relative to the picture of the program registered in the bookmark list. Then the program thus registered is received and displayed as a main picture in response to an actuation of a jump button switch, whereby any desired one of many broadcast channels can be selectively received with rapidity and certainty.

Abstract: A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.