Abstract: A semiconductor integrated circuit device includes an oscillator generating a clock signal and a charge pump circuit. The charge pump circuit includes capacity elements and an output transistor. The capacity element boosts a voltage on a boost node. The transistor (clamp circuit) clamps the voltage level on the boost node to a constant value. The capacity element controls the gate voltage of the output transistor. The clamp circuit is used to suppress a voltage applied to the transistors and the MOS capacity element, and suppresses generation of hot carriers.

Abstract: Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these subbanks, and internal read/write data buses are arranged in a region different from the region where the bank control circuits are arranged. Since there is no crossing of the bank control circuits and the internal read/write data buses, the bank control circuits can be efficiently arranged to reduce the layout area. Accordingly, a semiconductor integrated circuit device including multi-bank memories which operates stably at high speed can be provided without increase of an area occupied by a chip.

Abstract: For frequency change, the VCO is controlled through a sub-charge pump circuit to make a determination as to whether or not a difference of dividing data between before and after the change is within a predetermined range. When it is determined that the difference is outside the predetermined range, the loop filer is forcibly charged in a charge time which is determined proportional to the difference in the dividing data, to thereby control an oscillation frequency of the VOC. A large VOC oscillation frequency change can be swiftly realized. Also, while the frequency change circuit is controlling the oscillation frequency, a time constant of the loop filter in the PLL circuit is preferably set at a small value, so that frequency change by the frequency change circuit can be swiftly achieved.

Abstract: A DRAM control circuit or a test circuit describing a delay control cell is prepared. Automatic placement and routing is performed in relation to this circuit. Circuit simulation is executed at a step ST16. Delay control is performed with the delay control cell on the basis of a simulation result. Alternatively, delay control is performed with a circuit of the delay control cell on the basis of a test result. Thus, automatic placement and routing of at least either the DRAM control circuit or the test circuit provided in a DRAM is enabled.

Abstract: The DRAM macro includes a memory array having a plurality of memory cells, a read data line pair RDL provided extending in the column direction over the memory array, a read column decoder generating a column selection signal for selectively coupling the read data line pair RDL with a plurality of sense amplifiers, and a preamplifier for amplifying potential difference generated on the read data line pair RDL. The preamplifier and the read column decoder are arranged in areas opposite to each other with the memory array placed therebetween.

Abstract: A dynamic random access memory DRAM includes banks which are driven to active or inactive states independently of each other. Activation/inactivation of these banks are controlled by row controllers operating independently of each other, whereby a page or word line can be selected in each of the banks, a page hit rate can be increased, and the number of array precharge operation times in a page error as well as power consumption can be reduced in response. Thus, the cache hit rate of a processor having a built-in DRAM is increased and power consumption is reduced.

Abstract: A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.

Abstract: A first internal power supply circuit receiving an external power supply voltage for generating a first internal power supply voltage and a second internal power supply circuit receiving the external power supply voltage for generating a second internal power supply voltage are provided within a DRAM. A sense amplifier operates by the first internal power supply voltage. A write driver and a GIO line precharge circuit operate by the second internal power supply voltage. A peripheral circuit operates by the external power supply voltage. As a result, the sense amplifier and the peripheral circuit will not be affected by the operation of the write driver and the GIO line precharge circuit.

Abstract: A first memory of a large storage capacity is connected to a DQ pad for inputting and outputting an information signal through a bus interface unit. A first bidirectional transfer circuit and a second bidirectional transfer circuit for bidirectionally transmitting an information signal are provided between a high-speed memory and the memory of the large storage capacity. The first bidirectional transfer circuit is connected with the large storage capacity memory through a common bus, and the high-speed memory is interconnected with the second transfer circuit through a fifth bus. This second bidirectional transfer circuit is connected to an instruction register and a data register through a sixth bus. A processor is arranged in proximity to this instruction register and the data register, so that the processor processes an instruction from the instruction register and data from the data register and stores a processing result in the data register again.

Abstract: The paper for rolling a smoking article of the present invention contains particle-form calcium carbonate (30 to 60 wt %), calcined clay (5 to 30 wt %) and pulp. Furthermore, an alkaline metal salt is contained as a chemical additive. In addition, kaolin is contained in the paper. The basis weight of the paper falls within the range of 20 to 70 g/m.sup.2. Optical characteristics of the paper and the burning characteristics and ash characteristics of a cigarette are improved and the side stream smoke is reduced.

Abstract: Pre-amplifier circuits latch circuits, and output circuits respectively corresponding to a plurality of memory arrays are provided, and a data bus is provided common to these output circuits. The data bus provided extending in the column-direction over a memory array. Thus, a synchronous semiconductor memory device adapted for merging a logic and allowing the data bus width to be readily expanded without increasing the area occupied by interconnections and without conflicts of interconnections can be provided.

Abstract: Registers are arranged along at least opposite two sides of the four sides of a dynamic random access memory cell array. The registers are interconnected via an internal data bus line used for internal data transfer for the memory cell array. At least one register of the registers arranged along the opposite two sides is coupled with an external data bus, and the other register is coupled with an internal circuit via an internal data bus. An external controller which controls an operation in response to an external control signal is provided for the register coupled with an external circuit. An internal controller which controls an operation according to a control signal from the internal circuit is provided for the register coupled with the internal circuit. The external and internal circuits are permitted to simultaneously access the memory cell array only when the external and internal circuits read the data of a memory cell located at the same address of the memory cell array.

Abstract: An output buffer receives a voltage from a first power supply pin receiving an external power supply voltage for operation. Delay circuits included in an array control circuit, a read control circuit, a write control circuit and an internal clock generation circuit receive a voltage from a second power supply pin receiving the external power supply voltage for operation. Thus, a timing control is accurately performed for reading/writing a data signal without being affected by the change in power supply voltage due to an operation of the output buffer.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.