Abstract: An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.

Abstract: A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g.

Abstract: A method to resequence packets includes sequentially allocating in each source ingress adapter a packet rank to each packet received within each source ingress adapter. In each destination egress adapter, each ranked data packet is stored at a respective buffer address of an egress buffer. The respective buffer addresses of data packets received by a same source ingress adapter with a same priority level and switched through a same switching plane are linked in a same linked-list. The respective buffer addresses are preferably linked by their order of use in the egress buffer, and thus each linked-list is having a head list pointing to the oldest buffer address. The linked-lists are sorted into subsets including those linked-lists linking the respective buffer addresses of data packets received by a same source ingress adapter with a same priority level.

Abstract: A system for resequencing data packets is disclosed. In a preferred embodiment, the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter is further having a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location.

Abstract: A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides, at each packet cycle, a value N defining the priority rank to be read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm.

Abstract: A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank, and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides at each packet cycle a value N defining the priority rank to be considered by the queue scheduler whereby a data packet is read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm.

Abstract: A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.

Abstract: Methods and systems for analyzing the quality of high-speed signals are provided, wherein a high speed signal is sampled simultaneously a plurality of times during a sampling clock period at each of a plurality of phase rotator positions to generate a plurality of partial values, wherein subset pluralities of the partial values are associated to phase rotator positions. The partial values are combined into a global value which is analyzed to determine a quality of the high speed signal. Phase rotator behavior may also be analyzed to determine signal quality. A best position to lock a phase rotator when determining signal quality may be determined from a graphic characterization of a phase rotator position distribution.

Abstract: A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

Abstract: A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.

Abstract: A method and systems to test a communication system (200) comprising a plurality of emitters (205), receivers (210) and channels (220) are disclosed. According to the method of the invention the data used for the test are preprocessed so as to be analyzed on the fly by the receivers during the test. In a preferred embodiment, a connection identifier value characterizing emitter and receiver addresses as well as data properties, if any, is associated to each data and CRC bits are computed to format frames comprising data, connection identifier value and CRC bits (410). During the test, the communication system transmits frames from emitters to corresponding receivers. Upon frames reception, receivers extract data (455), connection identifier value (460) and CRC bits (465) and compute CRC bits on received data (470). The comparison (475) of transmitted and computed CRC bits in receiver allows determining whether or not frames have been well transmitted.

Abstract: A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

Abstract: A method and systems for analyzing the quality of high-speed signals, when signals can not be over-sampled due to sampler clock rates, is disclosed. According to the method of the invention, the position of a phase rotator is moved from one end to the other and data are sampled at each position (500). Then, data are formatted (505) to obtain a global value characterizing the signal behavior. Finally, this global value is corrected (510) to remove signal transition falsely detected too early. The use of the phase rotator multiplies artificially the number of sampling positions.

Abstract: The present invention concerns the use as perfuming ingredient of a lower alkyl ester of 4,6,6-trimethyl-1,3-cyclohexadiene-1-carboxylate or 4,6,6-trimethyl-3-cyclohexene-1-carboxylate. These compounds are able to impart odor notes of the spicy/saffron type.

Abstract: The present invention relates to a compound of formula wherein R represents a methyl or an ethyl group, in the form of any one of its isomers or of a mixture thereof. The invention relates also to the use of such a compound as a perfuming ingredient capable of imparting a odorant note of the rose type. Moreover, the invention concern also the perfumed article or perfuming composition containing a compound according to the invention.

Abstract: For switching or transmitting data packets, one can provide communication systems which consist of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master (21), the others are slave modules (22) controlled by control signals (25) derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

Abstract: A data switch is provided which routes fixed-size data packets from input ports to output ports, using shared memory which holds a copy of each packet in buffers. Output ports have a queue which contains pointers to buffers holding packets bound for that port. The number of shared memory buffers holding packets is compared to the number of buffer pointers in the output queues. In this way, a Multicast Index (MCI), a metric of the level of multicast traffic, is derived. The switch includes a Switch Core Adaptation Layer (SCAL) which has a multicast input queue. Because traffic is handled based on priority class P, a multicast threshold MCT(P), associated with the multicast input queue, is established per priority. While receiving traffic, the MCI is updated and, for each priority class in each SCAL, the MCI is compared to the MCT(P) to determine whether corresponding multicast traffic must be held.

Abstract: A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

Abstract: A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

Abstract: Congestion at an output from a node in a packet data communications network is controlled by maintaining a traffic profile based on the discardability/priority characteristics of recently received packets and by selecting at least an initial discard strategy which should be effective in ending congestion based on that profile. The profile is established by maintaining counts of the number of packets actually stored in an output buffer and of the number of packets which would have been stored if different discard strategies had been in force. The relationship of certain of the count values to a threshold determines which discard strategy is initially selected. Different, successively less intrusive discard strategies can be implemented until the congestion ends.