Abstract: The present invention relates to the use as a perfuming ingredient of 2-methyl-3-hexanone-oxime of formula in which the wavy line represents a bond having a configuration of the type (Z) or (E) or a mixture of the two configurations.

Abstract: A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g.

Abstract: A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time.

Abstract: A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion.

Abstract: A system and a method to avoid packet traffic congestion in a shared memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers and handling unicast as well as multicast traffic. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of data packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the memory shared switch core only if the switch core can send it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion.

Abstract: A system for resequencing data packets is disclosed. In a preferred embodiment, the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter is further having a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location.

Abstract: A method to resequence packets includes sequentially allocating in each source ingress adapter a packet rank to each packet received within each source ingress adapter. In each destination egress adapter, each ranked data packet is stored at a respective buffer address of an egress buffer. The respective buffer addresses of data packets received by a same source ingress adapter with a same priority level and switched through a same switching plane are linked in a same linked-list. The respective buffer addresses are preferably linked by their order of use in the egress buffer, and thus each linked-list is having a head list pointing to the oldest buffer address. The linked-lists are sorted into subsets including those linked-lists linking the respective buffer addresses of data packets received by a same source ingress adapter with a same priority level.

Abstract: A method and systems for analyzing the quality of high-speed signals, when signals can not be over-sampled due to sampler clock rates, is disclosed. According to the method of the invention, the position of a phase rotator is moved from one end to the other and data are sampled at each position (500). Then, data are formatted (505) to obtain a global value characterizing the signal behavior. Finally, this global value is corrected (510) to remove signal transition falsely detected too early. The use of the phase rotator multiplies artificially the number of sampling positions.

Abstract: A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

Abstract: The invention concerns (1-ethoxyethoxy-cyclododecane) which, although its smell is not noticed by a large number of people, can advantageously be used in a perfume composition as perfume exalting fixative.

Abstract: By appropriate arrangement of two sets of tables chosen to be complementary, cells which are conveyed through a first multiplexor, n RAM storages and the second are subject to a cell rearrange-ment enabling introduction of at least one bitmap field, thereby producing the n Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage, one particular byte is stored into one RAM available for a Write operation by use of the first set of tables, thereby causing an alteration to the normal association between the n RAMs and the n Logical Units which is then re-established by the second set of tables.

Abstract: A method and systems to test a communication system (200) comprising a plurality of emitters (205), receivers (210) and channels (220) are disclosed. According to the method of the invention the data used for the test are preprocessed so as to be analyzed on the fly by the receivers during the test. In a preferred embodiment, a connection identifier value characterizing emitter and receiver addresses as well as data properties, if any, is associated to each data and CRC bits are computed to format frames comprising data, connection identifier value and CRC bits (410). During the test, the communication system transmits frames from emitters to corresponding receivers. Upon frames reception, receivers extract data (455), connection identifier value (460) and CRC bits (465) and compute CRC bits on received data (470). The comparison (475) of transmitted and computed CRC bits in receiver allows determining whether or not frames have been well transmitted.

Abstract: A system for checking the integrity of data transfer in a switching element in a high speed packet switching network node where multicasting is performed by simultaneously shifting data from a first shift register into the targeted device shift registers. The outputs of the device registers are fed back into the first shift register. The checking system includes a device select circuit for selecting the targeted via a set of select lines and a negative OR gate circuit. The select line signals and the first register output are inputs to the OR gate, the output of which is fed back to the first register. A comparator circuit has inputs supplied by the device select lines and the outputs of the device registers. A processor compares the contents of the first register to the outputs from the logic comparator circuit to test whether the data has been properly multicast to the targeted.

Abstract: A Switch Fabric system comprising at least one Switch Fabric subsystem (100, 200) further including a set of Switch cores elements (111, 112, 121, 122) that are mounted in a port expansion permitting attachment of at least a first and second sets of Protocol Adapters (1, 2) under a routing control process. A Primary Switch controller (PSC) has a complete knowledge of the topology of the switch, e.g., the number of subsystems, the nature of the port expansion etc., while each Secondary Switch Controller only has a limited knowledge of that topology. One particular Switch Core (111, 211) which has a full-duplex communication capability in each Subsystem is assigned the key function to interface communication between the PSC and the other SSC in a same Switch Fabric Subsystem.

Abstract: A service message system for a switching architecture including at least one Switch Fabric (10, 20) comprising a switch core (15, 25) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the different Port adapters (30, 31). Each SCAL elements particularly includes a SCAL receive element (11-i) and a SCAL Xmit element (12-i) for the respective access to one input port and one output port via serial links. The service message is based on the use of a Cell qualifier field at the beginning of each cell, which comprises a first and a second field. The first field is the Filtering Control field which permits an easy decoding of a service message cell, when applicable. The second field is used for determining which particular type of service message is conveyed via the cell.

Abstract: The present invention proposes a device having a voice communication server structure comprising a rack called main rack including:

Abstract: A flow control process for a switching system having at least one switch core connected through serial communication links to remote and distributed Protocol Adapters or Protocol Engines through Switch Core Access Layer (SCAL) elements. For each input port i, the SCAL element contains a receive Protocol Interface corresponding to the adapter assigned to the input port i and a first serializer for providing attachment to the switch core by means of a first serial communication link. When the cells are received in the switch core, they are deserialized by means of a first deserializer. At each output port, the cells are serialized again by means of a second serializer and then transmitted via a second serial communication link, to the appropriate SCAL. The SCAL contains a second deserializer and a transmit Protocol Interface circuit for permitting attachment of the Protocol Adapter.

Abstract: A switching system having at least two switch fabrics. Each fabric has a switch core and a set of SCAL (Switch Core Access Layer) receive and transmit elements. The switch cores are preferably located in the same physical area but the SCALs may be distributed in different physical areas. Port Adapters distributed at different physical areas are connected to the switch fabrics via a particular SCAL element so that each switch core can receive cells from any port adapter and conversely any port adapter may receive data from either switch core. Control logic assigns a particular switch core to one port adapter for normal operations while reserving the other switch core for use when the first core is out of service. Each switch core has a mask mechanism which uses the value in a mask register to alter a bitmap value which controls the routing process. The mask registers in the two switch cores are loaded with complementary values.

Abstract: A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides, at each packet cycle, a value N defining the priority rank to be read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm.

Abstract: The present invention relates to a compound of formula 1