Patents by Inventor Alan Larson

Alan Larson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6349376
    Abstract: A method for providing the results of an address decode operation involves comparing the address of an address to be decoded with the address range containing an address previously decoded in a previous address decode operation, selecting the results of the previous address decode operation if the address of an address to be decoded is within the address range containing an address previously decoded in a previous address decode operation, and decoding the address to be decoded in a current address decode operation and selecting the results of the current address decode operation if the address containing an address to be decoded is not within the address range of an address previously decoded in a previous address decode operation.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: February 19, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Douglas Alan Larson
  • Patent number: 6321233
    Abstract: An apparatus is described for controlling pipelined memory access requests in a computer system. A graphics controller is coupled with a system memory by an AGP interface, which has separate write and read request queues. To control the ordering of the write and read requests relative to one another, each of the requests has an associated age tag assigned to it. In the event a read request is received by the AGP interface, an age tag value is assigned to it that corresponds with the number of previously received and currently pending write requests. Similarly, when a write request is received by the AGP interface, an age tag value is assigned that corresponds with the number of previously received and currently pending read requests. Employing such age tags provides AGP-compliant ordering of the write and read requests, while also providing write-passing-read capability without the attendant complex logic circuitry and time delays associated with conventional implementations.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: November 20, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Douglas Alan Larson
  • Patent number: 6292807
    Abstract: A method is described for controlling pipelined memory access requests in an AGP-compliant computer system. Memory access requests are stored in separate write and read request queues. To control the ordering of the write and read requests relative to one another, each of the requests has an associated age tag assigned to it. In the event a read request is received, an age tag value is assigned to it that corresponds with the number of previously received and currently pending write requests. Similarly, when a write request is received, an age tag value is assigned that corresponds with the number of previously received and currently pending read requests. Employing such age tags provides AGP-compliant ordering of the write and read requests, while also providing write-passing-read capability without the attendant complex logic circuitry and time delays associated with conventional AGP implementations.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: September 18, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Douglas Alan Larson
  • Patent number: 6026046
    Abstract: A logic device has address decoding logic for receiving an address to be decoded, for performing address decode operations and for providing current address decode operation results, an address range register for storing the address range of a previously decoded address, address comparing logic for comparing the address of the address to be decoded and the address range of the previously decoded address and selecting logic for bypassing a current address decode operation if the address of the address to be decoded is within the address range of the previously decoded address. The device may further have an address decode results register for storing the results of a previous address decode operation, wherein the selecting logic selects the results of the previous address decode operation stored in the address decode results register if the current address decode operation is bypassed.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: February 15, 2000
    Assignee: Micron Electronics, Inc.
    Inventor: Douglas Alan Larson