Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

Abstract: An integrated circuit (IC) fabrication flow including a multilevel metallization scheme wherein one or more metal layer members of a scribelane structure are formed according to one or more design constraints. A total thickness of the metal layer members of the scribelane structure along a dicing path may be limited to a threshold value to optimize dicing separation yields in a dicing operation.

Abstract: An integrated circuit with a first conductive region, a second conductive region, a plurality of dielectric layers of a first material type between the first conductive region and the second conductive region, and at least one dielectric layer of a second material type, between a first dielectric layer in the plurality of dielectric layers of a first material type and a second dielectric layer in the plurality of dielectric layers of the first material type. Each dielectric layer of a first material type has a thickness in a range from 0.5 ?m to 5.0 ?m, and the at least one dielectric layer of a second material type is not contacting a metal and has a thickness less than 2.0 ?m, and the second material type differs from the first material type in at least one of compression stress or elements in the first material type as compared to elements in the second material type.

Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

Abstract: A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.

Abstract: An electronic device has a conductive shield between first and second regions in a multilevel metallization structure, as well as a capacitor with first and second terminals in the first region, the first terminal laterally overlaps the second terminal by an overlap distance of 1.0 ?m to 6.0 ?m, the conductive shield includes a first metal line that encircles the first terminal, and the first metal line is spaced apart from the first terminal by a gap distance of 0.5 ?m to 1.0 ?m.

Abstract: A microelectronic device includes a semiconductor substrate and a high voltage isolation capacitor over the substrate. The capacitor includes a bottom capacitor plate over the substrate. Dielectric layers are formed above the bottom capacitor plate, including a top dielectric layer. A high dielectric layer on the top dielectric layer includes at least a first sublayer having a first dielectric constant that is higher than a dielectric constant of the top dielectric layer. A top capacitor plate is formed on the high dielectric layer over the bottom capacitor plate. An electric field abatement structure surrounds the top capacitor plate. The electric field abatement structure includes a shelf of the high dielectric layer extending outward from a lower corner of the bottom capacitor plate at least 14 microns, and an isolation break in the high dielectric layer past the shelf, in which the first sublayer is removed from the isolation break.

Abstract: A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.

Abstract: A method of assembling a structure, such as a wind turbine, is disclosed. The method comprises a step of providing a lifting arrangement comprising a gantry disposed over and/or directly above a rail, and lifting means coupled to the gantry. The method further comprises stacking portions of the structure by: conveyably disposing a first portion of the structure relative to the rail; lifting a second portion of the structure using the lifting means; disposing the first portion underneath the second portion by conveying the first portion along the rail; and lowering the second portion onto the first portion. Also disclosed is a corresponding system for assembling a structure, such as a wind turbine, and corresponding clamping and/or gripping system.

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

Abstract: Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery.

Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

Abstract: Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery.

Abstract: A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.

Abstract: The disclosed subject matter relates to a system and method for delivery of therapeutic agents across membranes such as to the inner ear. The system includes a plurality of microneedles that can be delivered to the round window membrane by a delivery device, e.g. catheter, and is capable of controlled penetration of the round window membrane to create temporary and self-closing perforations.

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

Abstract: An electrochemical system and process are provided to convert an amount of chalcopyrite (CuFeS2) to a product including copper ions. In an electrochemical reactor, a potential is applied across an anode and a cathode to convert the chalcopyrite to an intermediate, chalcocite (Cu2S). The anode is covered to prevent contact with the intermediate, thus limiting subsequent conversion of the intermediate to covellite (CuS) in favor of conversion to a material more suited to chemical oxidation, cuprite (Cu2O). For example, the anode can be covered with one or more layers of filter paper. Upon application of an oxidizing agent, the cuprite is oxidized to produce a product including copper ions. The cathode and covered anode allow for efficient and inexpensive processing. The cost of this technique is comparable to industry standards, and moreover, has a much smaller environmental footprint than heat-based copper extraction.

Abstract: An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.

Abstract: A method of assembling a structure, such as a wind turbine, is disclosed. The method comprises a step of providing a lifting arrangement comprising a gantry disposed over and/or directly above a rail, and lifting means coupled to the gantry. The method further comprises stacking portions of the structure by: conveyably disposing a first portion of the structure relative to the rail; lifting a second portion of the structure using the lifting means; disposing the first portion underneath the second portion by conveying the first portion along the rail; and lowering the second portion onto the first portion. Also disclosed is a corresponding system for assembling a structure, such as a wind turbine, and corresponding clamping and/or gripping system.

Abstract: Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.