Patents by Inventor Alan West

Alan West has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10629562
    Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Jason Chien, Byron Lovell Williams, Jeffrey Alan West, Anderson Li, Arvin Nono Verdeflor
  • Publication number: 20200058485
    Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 20, 2020
    Inventors: Jeffrey Alan West, Adrian Salinas, Elizabeth C. Stewart, Dhanoop Varghese, Thomas D. Bonifield
  • Publication number: 20200027848
    Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.
    Type: Application
    Filed: July 30, 2019
    Publication date: January 23, 2020
    Inventors: THOMAS DYER BONIFIELD, JEFFREY ALAN WEST, BYRON LOVELL WILLIAMS
  • Patent number: 10519469
    Abstract: Methods and systems for producing a biofuel using genetically modified sulfur-oxidizing and iron-reducing bacteria (SOIRB) are disclosed. In some embodiments, the methods include the following: providing a SOIRB that have been genetically modified to include a particular metabolic pathway to enable them to generate a biofuel; feeding a first source of ferric iron to the SOIRB; feeding sulfur, water, and carbon dioxide to the SOIRB; producing at least the first particular biofuel, a first source of ferrous iron, sulfate, excess ferric iron, and an SOIRB biomass; electrochemically reducing the excess ferric iron to a second source of ferrous iron; providing an iron-oxidizing bacteria that have been genetically modified to include a particular metabolic pathway to enable them to generate a second biofuel; producing at least the second biofuel, a second source of ferric iron, and an IOB biomass; and feeding the second source of ferric iron to the SOIRB.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: December 31, 2019
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Scott Banta, Alan West, Timothy Kernan
  • Patent number: 10366958
    Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas Dyer Bonifield, Jeffrey Alan West, Byron Lovell Williams
  • Publication number: 20190206812
    Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: THOMAS DYER BONIFIELD, JEFFREY ALAN WEST, BYRON LOVELL WILLIAMS
  • Publication number: 20190206828
    Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Application
    Filed: July 2, 2018
    Publication date: July 4, 2019
    Inventors: Honglin GUO, Jason CHIEN, Byron Lovell WILLIAMS, Jeffrey Alan WEST, Anderson LI, Arvin Nono VERDEFLOR
  • Publication number: 20190198604
    Abstract: Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Elizabeth C. Stewart, Jeffrey Alan West, Thomas D. Bonifield, Jay Sung Chun, Byron Lovell Williams
  • Publication number: 20190137162
    Abstract: A dynamic packing system places one or more perishable items into a shipping container and dispenses thermal control components therein. There is a data processor and a database including one or more order data set each defined at least by an itemized list of purchased perishable items and an order shipment destination address. A network interface is connected to the data processor, and weather data is retrieved over the network interface from a remote source. A dispenser controlled by the data processor positions a specific amount of a thermal control component in the shipping container. The specific amount is based upon an evaluation of one or more temperature values corresponding to the weather data along a transport route of the shipping container.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 9, 2019
    Inventors: Dave Ominsky, Brian Wallin, John Grogg, Kyle Hoberg, Alan West
  • Publication number: 20190074350
    Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.
    Type: Application
    Filed: November 1, 2018
    Publication date: March 7, 2019
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams
  • Patent number: 10147784
    Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams
  • Patent number: 10109597
    Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: October 23, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Basab Chatterjee
  • Publication number: 20180195090
    Abstract: Methods and systems for producing a biofuel using genetically modified sulfur-oxidizing and iron-reducing bacteria (SOIRB) are disclosed. In some embodiments, the methods include the following: providing a SOIRB that have been genetically modified to include a particular metabolic pathway to enable them to generate a biofuel; feeding a first source of ferric iron to the SOIRB; feeding sulfur, water, and carbon dioxide to the SOIRB; producing at least the first particular biofuel, a first source of ferrous iron, sulfate, excess ferric iron, and an SOIRB biomass; electrochemically reducing the excess ferric iron to a second source of ferrous iron; providing an iron-oxidizing bacteria that have been genetically modified to include a particular metabolic pathway to enable them to generate a second biofuel; producing at least the second biofuel, a second source of ferric iron, and an IOB biomass; and feeding the second source of ferric iron to the SOIRB.
    Type: Application
    Filed: July 26, 2017
    Publication date: July 12, 2018
    Applicant: The Trustees of Columbia University in the City of New York
    Inventors: Scott Banta, Alan West, Timothy Kernan
  • Publication number: 20180144307
    Abstract: A notification system and method that allows a user to be placed on a waiting list, disclosing only the personal information the user chooses to disclose, and receive updates or other information relating to his status on the waiting list through a personal communication device. A timekeeping system and method generates time in and time out record entries based upon a display code presented the personal communication device. A form data aggregation system and method consolidates inputted information from multiple applications on the personal communication device.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventor: Alan West
  • Publication number: 20170308821
    Abstract: A notification system and method that allows a user to be placed on a waiting list, disclosing only the personal information the user chooses to disclose, and receive updates or other information relating to his status on the waiting list through a personal communication device.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventor: Alan West
  • Publication number: 20170309702
    Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.
    Type: Application
    Filed: July 11, 2017
    Publication date: October 26, 2017
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams
  • Patent number: 9768245
    Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: September 19, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams
  • Publication number: 20170263696
    Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams
  • Patent number: 9745601
    Abstract: Methods and systems for producing a biofuel using genetically modified sulfur-oxidizing and iron-reducing bacteria (SOIRB) are disclosed. In some embodiments, the methods include the following: providing a SOIRB that have been genetically modified to include a particular metabolic pathway to enable them to generate a biofuel; feeding a first source of ferric iron to the SOIRB; feeding sulfur, water, and carbon dioxide to the SOIRB; producing at least the first particular biofuel, a first source of ferrous iron, sulfate, excess ferric iron, and an SOIRB biomass; electrochemically reducing the excess ferric iron to a second source of ferrous iron; providing an iron-oxidizing bacteria that have been genetically modified to include a particular metabolic pathway to enable them to generate a second biofuel; producing at least the second biofuel, a second source of ferric iron, and an IOB biomass; and feeding the second source of ferric iron to the SOIRB.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: August 29, 2017
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Scott Banta, Alan West, Timothy Kernan
  • Patent number: 9741787
    Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 22, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams