Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract: Circuitry is disclosed that includes a first conductive portion of a first die and a first conductive pillar electrically and physically connected to the first conductive portion. The first conductive pillar includes a first conductive pillar surface. A first bond connects the first conductive pillar surface to a first end of a bond wire.

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Abstract: Methods and systems for producing a particular biofuel or a particular chemical using genetically modified iron-oxidizing bacteria (IOB) and copper as a redox mediator are disclosed. In some embodiments, the methods include the following: providing an IOB that have been genetically modified to enable them to generate the particular biofuel or the particular chemical; feeding a first source of ferrous iron to the IOB; feeding water, carbon dioxide, and oxygen to the IOB; producing one of the particular biofuel and the particular chemical, ferric iron, and an IOB biomass; providing a first source of copper metal; solubilizing the first source of copper metal to produce cupric ions and reduce the ferric iron to ferrous iron; electrochemically reducing the cupric ions to produce a second source of copper metal; feeding ferrous iron reduced from the ferric iron to the IOB; and feeding the second source of copper metal to the IOB.

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract: The invention relates to a crane, such as a hoisting crane (3000) having a hoisting boom (3010) having a lifting region (3020), configured to lift a load (3050) and an actuatable restraint device (3040), the device extending from the crane. The actuatable restraint device is configured to engage with a load being lifted, so as to control movement of that load with respect to the lifting region in at least one direction. The actuatable restraint device may be configured to control movement in as much as inhibiting, or mitigating, certain movement.

Abstract: The invention relates to structures, such as offshore structures, associated apparatus and methods. For example, the invention can relate to wind turbine structures, such as piles for offshore wind turbines, and associated apparatus and methods. In some examples, the invention relates to guide apparatus for offshore piles having a guide portion configured to provide an acoustic barrier between a pile and a surrounding body of water during deployment of a pile at a body of water. The apparatus may comprise a dampening structure, such as inflatable bladders, or the like, configured to provide the acoustic barrier. In some example, the guide apparatus comprises a piling template, configured to be positioned on a water floor, so that the guide portion can locate, and be positioned with, the template to allow for guiding of a pile to a water floor.

Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.

Abstract: Methods and systems for producing a biofuel using genetically modified sulfur-oxidizing and iron-reducing bacteria (SOIRB) are disclosed. In some embodiments, the methods include the following: providing a SOIRB that have been genetically modified to include a particular metabolic pathway to enable them to generate a biofuel; feeding a first source of ferric iron to the SOIRB; feeding sulfur, water, and carbon dioxide to the SOIRB; producing at least the first particular biofuel, a first source of ferrous iron, sulfate, excess ferric iron, and an SOIRB biomass; electrochemically reducing the excess ferric iron to a second source of ferrous iron; providing an iron-oxidizing bacteria that have been genetically modified to include a particular metabolic pathway to enable them to generate a second biofuel; producing at least the second biofuel, a second source of ferric iron, and an IOB biomass; and feeding the second source of ferric iron to the SOIRB.

Abstract: A notification system and method that allows a user to be placed on a waiting list, disclosing only the personal information the user chooses to disclose, and receive updates or other information relating to his status on the waiting list through a personal communication device.

Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.

Abstract: Methods and systems for producing a biofuel using genetically modified iron-oxidizing bacteria (IOB) are disclosed. In some embodiments, the methods include the following: providing an IOB that have been genetically modified to enable them to generate a biofuel or chemical; feeding a first source of ferrous iron to the IOB; feeding water, carbon dioxide, and oxygen to the IOB; producing at least the biofuel or chemical, ferric iron, and an IOB biomass; and preventing ferric precipitates from forming. In some embodiments, the methods and systems include the following: a bioreactor including IOB that have been genetically modified to enable them to generate a biofuel; a first source of ferrous iron; sources of water, carbon dioxide, and oxygen; a source of anti-ferric precipitating agent in fluid communication with the bioreactor; and a electrochemical reactor that is configured to electrochemically reduce ferric iron to a second source of ferrous iron.

Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

Abstract: A through-substrate via (TSV) die includes a substrate with a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface. A plurality of TSVs extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface and include an inner metal core of electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for the TSVs. A tip deformation protecting layer of inorganic dielectric material is on the bottom side surface lateral to the TSV tips. An elastic modulus of the inorganic dielectric material is greater than (>) an elastic modulus of the electrically conductive filler material. A second dielectric layer including a polymer is on the tip deformation protecting layer.

Abstract: A through-substrate via (TSV) die includes a substrate having a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface, wherein the layers on the top side semiconductor surface exert a net tensile stress to the top side semiconductor surface. A plurality of TSVs which extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface include an inner metal core surrounded by a dielectric liner that forms an outer edge for the TSVs. A dielectric stack is on the bottom side surface lateral to the TSV tips including a compressive dielectric layer and a tensile dielectric layer on the compressive dielectric layer.