Patents by Inventor Alberto Valdes

Alberto Valdes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150341011
    Abstract: A reconfigurable rat race coupler and methods of designing and reconfiguring the rat race coupler are disclosed. The reconfigurable rat race coupler, includes a plurality of transmission lines. The plurality of transmission lines include: a first transmission line and a second transmission line each of which comprise a phase shifter; and a third transmission line and a fourth transmission line each of which comprise phase shifters. A signal input on port 1 is provided between the phase shifters on the third transmission line, which is split between ports 2 and 3, with port 4 being isolated and port 2 being between the phase shifters on the fourth transmission line.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 26, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hanyi DING, Alberto VALDES GARCIA, Wayne H. WOODS, JR.
  • Publication number: 20150341009
    Abstract: A reconfigurable bandstop filter and methods of designing and reconfiguring the bandstop filter are disclosed. The reconfigurable bandstop filter includes a plurality of transmission lines each including a phase shifter. The reconfigurable bandstop filter further includes a signal input port having a phase shifter and a signal output port having a phase shifter. The signal input port and the signal output port is coupled to the plurality of transmission lines.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 26, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hanyi DING, Alberto VALDES GARCIA, Wayne H. WOODS, JR.
  • Publication number: 20150333051
    Abstract: An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 19, 2015
    Inventors: David R. Greenberg, Jean-Olivier Plouchart, Alberto Valdes-Garcia
  • Patent number: 9191057
    Abstract: A polarimetric transceiver front-end includes two receive paths configured to receive signals from an antenna, each receive path corresponding to a respective polarization. Each front-end includes a variable amplifier and a variable phase shifter; a first transmit path configured to send signals to the antenna, where the transmit path is connected to the variable phase shifter of one of the two receive paths and includes a variable amplifier; and a transmit/receive switch configured to select between the first transmit path and the two receive paths for signals, where the transmit/receive switch includes a quarter-wavelength transmission line that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: November 17, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herschel A. Ainspan, Mark Ferriss, Arun S. Natarajan, Benjamin D. Parker, Jean-Oliver Plouchart, Scott K. Reynolds, Mihai A. Sanduleanu, Alberto Valdes Garcia
  • Patent number: 9190951
    Abstract: There is provided an integrated electronic circuit. The integrated electronic circuit includes a voltage controlled oscillator and a frequency doubler connected to the voltage controlled oscillator. A frequency doubling input of the frequency doubler is load isolated from an output of the voltage controlled oscillator.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: November 17, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bodhisatwa Sadhu, Mihai A. Sanduleanu, Alberto Valdes Garcia, Scott K. Reynolds
  • Patent number: 9190479
    Abstract: An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: David R. Greenberg, Jean-Olivier Plouchart, Alberto Valdes-Garcia
  • Patent number: 9174413
    Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than >1e1013 cm?2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm?2>n>0 cm?2, which is effective to absorb the electromagnetic radiation.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Phaedon Avouris, Alberto Valdes Garcia, Chun-Yung Sung, Fengnian Xia, Hugen Yan
  • Patent number: 9170439
    Abstract: A method for controlling an electro-optic modulator device includes measuring a performance metric of the device to define a first measured performance value, and changing a state of a first tuning portion of the device to connect the first tuning portion to ground.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Gill, William M. Green, Alberto Valdes Garcia
  • Publication number: 20150303548
    Abstract: A reconfigurable branch line coupler and methods of designing and reconfiguring the branch line coupler are disclosed. The reconfigurable branch line coupler includes a plurality of transmission lines, each of which comprises a phase shifter. The reconfigurable branch line coupler further includes an input port, which is split into two quadrature signals providing a second and third port between adjacent of the plurality of transmission lines, with a fourth port isolated from the input port at a center frequency.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 22, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hanyi DING, Alberto VALDES GARCIA, Wayne H. WOODS, JR.
  • Publication number: 20150288077
    Abstract: Systems, methods, devices and apparatuses directed to transceiver devices are disclosed. In accordance with one method, a first set of antenna positions in a first section of a set of sections of a circuit layout for the circuit package is selected. The method further includes selecting another set of antenna positions in another section of the circuit layout such that an arrangement of selected antenna positions of the other set is different from an arrangement of selected antenna positions of a previously selected set of antenna positions. The selecting another set of positions in another section is iterated until selections have been made for a total number of antennas. The selecting the other set is performed such that consecutive unselected positions in the other section do not exceed a predetermined number of positions. In addition, antenna elements are formed at the selected positions to fabricate the circuit package.
    Type: Application
    Filed: May 29, 2015
    Publication date: October 8, 2015
    Inventors: Daniel J. Friedman, Xiaoxiong Gu, Duixian Liu, Arun S. Natarajan, Scott K. Reynolds, Alberto Valdes Garcia
  • Patent number: 9147752
    Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: September 29, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shu-Jen Han, Alberto Valdes Garcia
  • Patent number: 9134481
    Abstract: A signal transfer link includes a first plasmonic coupler, and a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap. An insulator layer is formed over end portions of the first and second plasmonic couplers and in and over the gap. A plasmonic conductive layer is formed over the gap on the insulator layer to excite plasmons to provide signal transmission between the first and second plasmonic couplers.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 15, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Phaedon Avouris, Vasili Perebeinos, Mathias B. Steiner, Alberto Valdes Garcia
  • Publication number: 20150255631
    Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.
    Type: Application
    Filed: May 22, 2015
    Publication date: September 10, 2015
    Inventors: ZHIHONG CHEN, SHU-JEN HAN, SIYURANGA O. KOSWATTA, ALBERTO VALDES GARCIA
  • Publication number: 20150244320
    Abstract: An apparatus comprises a resonator including a plurality of switched impedances spatially distributed within the resonator and a corresponding plurality of transconductance elements distributed within respective distances among the switched impedances. The resonator has a given desired resonant frequency and a given amplitude of response. Combined pairs of the switched impedances and transconductance elements have respective parasitic resonant frequencies which are higher than the given desired resonant frequency and have respective amplitudes of response which are lower than the given amplitude of response. The apparatus may be a voltage controlled oscillator or an active filter.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: International Business Machines Corporation
    Inventors: MARK A. FERRISS, Daniel J. Friedman, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes Garcia
  • Patent number: 9093949
    Abstract: There is provided an integrated electronic circuit. The integrated electronic circuit includes a voltage controlled oscillator and a frequency doubler connected to the voltage controlled oscillator. A frequency doubling input of the frequency doubler is load isolated from an output of the voltage controlled oscillator.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bodhisatwa Sadhu, Mihai A. Sanduleanu, Alberto Valdes Garcia, Scott K. Reynolds
  • Publication number: 20150200676
    Abstract: Methods and systems for phase correction include determining a phase error direction and generating a prediction for the phase error based on a sigma-delta error. It is determined whether the prediction agrees with the determined phase error direction. If the prediction does not agree, a phase correction is adjusted in accordance with the predicted phase error.
    Type: Application
    Filed: September 25, 2014
    Publication date: July 16, 2015
    Inventors: HERSCHEL A. AINSPAN, MARK A. FERRISS, DANIEL J. FRIEDMAN, ALEXANDER V. RYLYAKOV, BODHISATWA SADHU, ALBERTO VALDES GARCIA
  • Publication number: 20150200677
    Abstract: Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two output signals. A difference in time between pulse widths of the two output signals corresponds to a phase difference between the reference clock and the feedback clock. A programmable delay line is configured to delay an earlier output signal in accordance with a predicted deterministic phase error. An oscillator is configured to generate a feedback signal in accordance with the delayed output signal. A divider is configured to divide a frequency of the oscillator output by an integer N. The integer N is varied to achieve an average fractional divide ratio and the predicted deterministic phase error is based on the average divide ratio and an instantaneous divide ratio.
    Type: Application
    Filed: September 26, 2014
    Publication date: July 16, 2015
    Inventors: HERSCHEL A. AINSPAN, MARK A. FERRISS, DANIEL J. FRIEDMAN, ALEXANDER V. RYLYAKOV, BODHISATWA SADHU, ALBERTO VALDES GARCIA
  • Publication number: 20150200627
    Abstract: A voltage controlled oscillator (VCO), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the VCO comprises an LC tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit. The VCO further comprises a supply node, a tail node, and a noise by-pass circuit connected to the supply and tail nodes, in parallel with the tank circuit and the oscillator core. The by-pass circuit forms a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 16, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alberto Valdes-Garcia, Bodhisatwa Sadhu
  • Patent number: 9059679
    Abstract: Tunable interconnect structures, integrated circuits containing the tunable interconnect structures and methods of manufacturing the same are disclosed. The interconnect transmission line structure includes a signal conductor and a plurality of conductors in proximity to the signal conductor. The structure further includes one or more switchable conductors in proximity to at least the signal conductor. The one or more switchable conductors has a programmable wiring switch with a terminal connected to the one or more switchable conductors and another terminal connected to ground.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: June 16, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Alberto Valdes-Garcia, Stephen M. Gates, Wayne H. Woods, Jr.
  • Publication number: 20150155858
    Abstract: Methods for frequency multiplying include receiving a signal having an input frequency at a frequency multiplier comprising a pair of transistors; and selecting a harmonic in the signal by connecting the transistors to a common impedance through a respective collector impedance, wherein an output frequency at the harmonic between the collector impedances and the common impedance is an even integer multiple of an input frequency.
    Type: Application
    Filed: February 9, 2015
    Publication date: June 4, 2015
    Inventors: WOORAM LEE, ALBERTO VALDES GARCIA