Patents by Inventor Alex See

Alex See has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9620418
    Abstract: Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Liang Li, Wei Lu, Lian Choo Goh, Yung Fu Alfred Chong, Fangyue Liu, Alex See
  • Patent number: 9548371
    Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: January 17, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jingyan Huang, Chuan Wang, Chim Seng Seet, Yun Ling Tan, Alex See
  • Patent number: 9543502
    Abstract: A method of forming high density contact array is disclosed. The method includes providing a first dielectric layer and forming a hard mask stack over the first dielectric layer. The hard mask stack includes first, second and third hard mask layers. The first and second hard mask layers are processed to form high density array of hard mask stack structures using a double patterning process. The hard mask stack structures include patterned first and second hard mask layers having a first width F1. The width of the patterned second hard mask layers is reduced to a second width F2 to form high density array of hard mask posts. A fourth hard mask layer is formed over the third hard mask layer and surrounding the hard mask posts. The hard mask posts and portions of the third hard mask layer and first dielectric layer underlying the hard mask posts are removed to form high density contact hole array.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zheng Zou, Alex See
  • Patent number: 9537092
    Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a lower electrode overlying a substrate, an insulating layer overlying the lower electrode, and an upper electrode overlying the insulating layer. The lower electrode, the insulating layer, and the upper electrode form a stack having a side surface. A phase change spacer is adjacent to the side surface, where the phase change spacer is electrically connected to the lower electrode and the upper electrode.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zheng Zou, Alex See, Shyue Seng Tan
  • Patent number: 9520371
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 13, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benfu Lin, Wanbing Yi, Wei Lu, Alex See, Juan Boon Tan
  • Patent number: 9511474
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benfu Lin, Wei Lu, Alex See
  • Patent number: 9511470
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benfu Lin, Lei Wang, Xuesong Rao, Wei Lu, Alex See
  • Publication number: 20160351507
    Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer overlying the base dielectric layer, and a second dielectric layer overlying the first dielectric layer. A first overlay mark is positioned within the first dielectric layer, and a second overlay mark is positioned within the second dielectric layer, where the second overlay mark is offset from the first overlay mark. First and second blocks are positioned within the base dielectric layer, where the first overlay mark directly overlays the first block and the second overlay mark directly overlays the second block.
    Type: Application
    Filed: May 26, 2015
    Publication date: December 1, 2016
    Inventors: Shijie Wang, Yong Feng Fu, Siew Yong Leong, Lei Wang, Alex See
  • Publication number: 20160351791
    Abstract: A method of forming high density contact array is disclosed. The method includes providing a first dielectric layer and forming a hard mask stack over the first dielectric layer. The hard mask stack includes first, second and third hard mask layers. The first and second hard mask layers are processed to form high density array of hard mask stack structures using a double patterning process. The hard mask stack structures include patterned first and second hard mask layers having a first width F1. The width of the patterned second hard mask layers is reduced to a second width F2 to form high density array of hard mask posts. A fourth hard mask layer is formed over the third hard mask layer and surrounding the hard mask posts. The hard mask posts and portions of the third hard mask layer and first dielectric layer underlying the hard mask posts are removed to form high density contact hole array.
    Type: Application
    Filed: May 25, 2015
    Publication date: December 1, 2016
    Inventors: Zheng ZOU, Alex SEE
  • Publication number: 20160284991
    Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a lower electrode overlying a substrate, an insulating layer overlying the lower electrode, and an upper electrode overlying the insulating layer. The lower electrode, the insulating layer, and the upper electrode form a stack having a side surface. A phase change spacer is adjacent to the side surface, where the phase change spacer is electrically connected to the lower electrode and the upper electrode.
    Type: Application
    Filed: March 23, 2015
    Publication date: September 29, 2016
    Inventors: Zheng Zou, Alex See, Shyue Seng Tan
  • Patent number: 9437547
    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benfu Lin, Hong Yu, Lup San Leong, Alex See, Wei Lu
  • Publication number: 20160233157
    Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Inventors: Yeow Kheng LIM, Alex SEE, Tae Jong LEE, David VIGAR, Liang Choo HSIA, Kin Leong PEY
  • Publication number: 20160190066
    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.
    Type: Application
    Filed: March 8, 2016
    Publication date: June 30, 2016
    Inventors: Benfu LIN, Hong YU, Lup San LEONG, Alex SEE, Wei LU
  • Patent number: 9349654
    Abstract: Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Liang Li, Xuesong Rao, Martina Damayanti, Wei Lu, Alex See, Yoke Leng Lim
  • Publication number: 20160136781
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.
    Type: Application
    Filed: January 25, 2016
    Publication date: May 19, 2016
    Inventors: Benfu Lin, Wei Lu, Alex See
  • Publication number: 20160136774
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.
    Type: Application
    Filed: January 25, 2016
    Publication date: May 19, 2016
    Inventors: Benfu LIN, Lei WANG, Xuesong RAO, Wei LU, Alex SEE
  • Publication number: 20160133524
    Abstract: Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 12, 2016
    Inventors: Liang Li, Wei Lu, Lian Choo Goh, Yung Fu Alfred Chong, Fangyue Liu, Alex See
  • Publication number: 20160118355
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 28, 2016
    Inventors: Benfu LIN, Wanbing YI, Wei LU, Alex SEE, Juan Boon TAN
  • Publication number: 20160114457
    Abstract: A polishing pad for use in chemical mechanical polishing of a substrate is disclosed. The polishing pad includes first and second major surfaces. The first major surface forms a polishing surface and is divided into a main portion and edge portions. The edge portions are nearer to edges of the polishing pad while the main portion is between the edge portions and farther from the edges of the polishing pad. The polishing pad also includes a plurality of polishing posts disposed on the first major surface of the pad. The densities of the polishing posts in the edge portions and main portion are different.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 28, 2016
    Inventors: Lup San LEONG, Cing Gie LIM, Wei LU, Ming ZENG, Alex SEE
  • Patent number: 9318378
    Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.
    Type: Grant
    Filed: August 21, 2004
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yeow Kheng Lim, Alex See, Tae Jong Lee, David Vigar, Liang Choo Hsia, Kin Leong Pey