Patents by Inventor Alex See

Alex See has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070066047
    Abstract: A method for forming an opening on a material layer is provided. First, a dielectric layer is formed on the material layer. Then, a metallic hard mask layer and a cap layer are sequentially formed on the dielectric layer. Thereafter, a patterned photoresist layer is formed on the cap layer. The patterned photoresist layer exposes a portion of the surface of the cap layer. After that, a first etching operation is carried out using the patterned photoresist layer as a mask to remove a portion of the cap layer and the metallic hard mask layer until the surface of the dielectric layer is exposed. Then, the photoresist layer is removed. A second etching operation is carried out using the cap layer and the metallic hard mask layer as a mask to remove a portion of the dielectric layer and form an opening.
    Type: Application
    Filed: September 18, 2005
    Publication date: March 22, 2007
    Inventors: Jianhui Ye, Kai Hung Alex See, Tien-Cheng Lan, Meisheng Zhou
  • Publication number: 20060286797
    Abstract: Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Inventors: Fan Zhang, Kho Liep, Alex See, Cheng-Cheh Tou, Xiaomei Bu, Tae Lee, Liang Hsia
  • Patent number: 7119010
    Abstract: An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: October 10, 2006
    Assignee: Chartered Semiconductor Manfacturing Ltd.
    Inventors: Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Wang Ling Goh
  • Patent number: 7112499
    Abstract: A process is described to form a semiconductor device such as MOSFET or CMOS with shallow junctions in the source/drain extension regions. After forming the shallow trench isolations and the gate stack, sidewall dielectric spacers are removed. A pre-amorphizing implant (PAI) is performed with Ge+ or Si+ ions to form a thin PAI layer on the surface of the silicon regions adjacent to the gate stack. B+ ion implantation is then performed to form source/drain extension (SDE) regions. The B+ implant step is then followed by multiple-pulsed 248 nm KrF excimer laser anneal with pulse duration of 23 ns. This step is to reduce the sheet resistance of the junction through the activation of the boron dopant in the SDE junctions. Laser anneal is then followed by rapid thermal anneal (RTA) to repair the residual damage and also to induce out-diffusion of the boron to yield shallower junctions than the just-implanted junctions prior to RTA.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: September 26, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chyiu Hyia Poon, Leng Seow Tan, Byung Jin Cho, Alex See, Mousumi Bhat
  • Patent number: 7094669
    Abstract: A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: August 22, 2006
    Assignee: Chartered Semiconductor Manufacturing LTD
    Inventors: Xiaomei Bu, Alex See, Tae Jong Lee, Fan Zhang, Yeon Kheng Lim, Liang Choo Hsia
  • Patent number: 7091092
    Abstract: A method for forming a self-aligned, recessed channel, MOSFET device that alleviates problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A thin pad oxide layer is grown overlying the substrate and a gate recess, followed by deposition of a thick silicon nitride layer filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown, thickening the pad oxide layer. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is removed. The oxide layer at the bottom of the gate recess is removed and a gate dielectric layer is grown. Gate polysilicon is deposited filling the gate recess. S/D implantations, metallization, and passivation complete fabrication of the device.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: August 15, 2006
    Assignees: Chartered Semiconductor Manufacturing Ltd., National University of Singapore
    Inventors: Sneedharan Pillai Sneelal, Francis Poh, James Lee, Alex See, C. K. Lau, Ganesh Shankar Samudra
  • Patent number: 7030451
    Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: April 18, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Pooi See Lee, Kin Leong Pey, Alex See, Lap Chan
  • Publication number: 20060040491
    Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.
    Type: Application
    Filed: August 21, 2004
    Publication date: February 23, 2006
    Inventors: Yeow Lim, Alex See, Tae Lee, David Vigar, Liang Hsia, Kin Pey
  • Publication number: 20060030128
    Abstract: A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.
    Type: Application
    Filed: August 3, 2004
    Publication date: February 9, 2006
    Inventors: Xiaomei Bu, Alex See, Tae Lee, Fan Zhang, Yeon Lim, Liang Hsia
  • Publication number: 20050158956
    Abstract: A process is described to form a semiconductor device such as MOSFET or CMOS with shallow junctions in the source/drain extension regions. After forming the shallow trench isolations and the gate stack, sidewall dielectric spacers are removed. A pre-amorphizing implant (PAI) is performed with Ge+ or Si+ ions to form a thin PAI layer on the surface of the silicon regions adjacent to the gate stack. B+ ion implantation is then performed to form source/drain extension (SDE) regions. The B+ implant step is then followed by multiple-pulsed 248 nm KrF excimer laser anneal with pulse duration of 23 ns. This step is to reduce the sheet resistance of the junction through the activation of the boron dopant in the SDE junctions. Laser anneal is then followed by rapid thermal anneal (RTA) to repair the residual damage and also to induce out-diffusion of the boron to yield shallower junctions than the just-implanted junctions prior to RTA.
    Type: Application
    Filed: January 16, 2004
    Publication date: July 21, 2005
    Inventors: Chyiu Poon, Leng Tan, Byung Cho, Alex See, Mousumi Bhat
  • Publication number: 20050156269
    Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature.
    Type: Application
    Filed: March 15, 2005
    Publication date: July 21, 2005
    Inventors: Pooi Lee, Kin Pey, Alex See, Lap Chan
  • Patent number: 6905964
    Abstract: An improved and new process for fabricating self-aligned metal barriers by atomic layer deposition, ALD, capable of producing extremely thin, uniform, and conformal metal barrier films, selectively depositing on copper, not on silicon dioxide interlevel dielectric, in multi-layer dual damascene trench/via processing. Silicon nitride is presently used as a insulating copper barrier. However, silicon nitride has a relatively high dielectric constraint, which deteriorates ICs with increased RC delay. Copper metal barriers of niobium and tantalum have been deposited by atomic layer deposition on copper. With high deposition selectivity, the barrier metal is only deposited over copper, not on silicon dioxide, which eliminates the need of an insulating barrier of silicon nitride.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: June 14, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Boon Kiat Lim, Alex See
  • Patent number: 6899857
    Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of preparing a microemulsion. The method of the present embodiment then recites applying the microemulsion to a surface above which it is desired to form a region of low dielectric constant nanoporous material. Next, the present method recites subjecting the microemulsion, which has been applied to the surface, to a thermal process such that the region of low dielectric constant nanoporous material is formed above the surface.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: May 31, 2005
    Assignee: Chartered Semiconductors Manufactured Limited
    Inventors: Soo Choi Pheng, Lap Chan, Wang Cui Yang, Siew Yong Kong, Alex See
  • Patent number: 6897118
    Abstract: A method for forming a highly activated ultra shallow ion implanted semiconductive elements for use in sub-tenth micron MOSFET technology is described. A key feature of the method is the ability to activate the implanted impurity to a highly active state without permitting the dopant to diffuse further to deepen the junction. A selected single crystalline silicon active region is first amorphized by implanting a heavy ion such as silicon or germanium. A semiconductive impurity for example boron is then implanted and activated by pulsed laser annealing whereby the pulse fluence, frequency, and duration are chosen to maintain the amorphized region just below it's melting temperature. It is found that just below the melting temperature there is sufficient local ion mobility to secure the dopant into active positions within the silicon matrix to achieve a high degree of activation with essentially no change in concentration profile.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: May 24, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chyiu-Hyia Poon, Byung Jin Cho, Yong Feng Lu, Alex See, Mousumi Bhat
  • Patent number: 6890854
    Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: May 10, 2005
    Assignee: Chartered Semiconductor Manufacturing, Inc.
    Inventors: Pooi See Lee, Kin Leong Pey, Alex See, Lap Chan
  • Patent number: 6878623
    Abstract: A gate structure having associated (LDD) regions and source and drain is formed as is conventional. A first oxide spacer, for example, is formed along the sidewalls of the gate structure. A layer of metal such as titanium is then deposited over the surface of the gate structure. Second sidewall spacers are formed covering the metal over the first sidewall spacer and covering the metal over isolation regions. A layer of polysilicon is deposited over the surface of the gate structure. A rapid thermal annealing (RTA) is performed causing the metal to react with both the silicon in the junction below the metal and the polysilicon above the metal forming a metal silicide. Metal along the sidewalls between the first and second sidewall spacers and over the isolation regions does not react and is etched away. By providing an additional source of silicon in the polysilicon layer above the metal, a thicker silicide is achieved.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: April 12, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Cheng Cheh Tan, Randall Cher Liang Cha, Alex See, Lap Chan
  • Patent number: 6849928
    Abstract: A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: February 1, 2005
    Assignee: Chartered Semiconductor Manufacturing, LTD
    Inventors: Randall Cher Liang Cha, Yeow Kheng Lim, Alex See, Tae Jong Lee, Wang Ling Goh
  • Patent number: 6777329
    Abstract: A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: August 17, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd
    Inventors: Shaoyin Chen, Ze Xiang Shen, Alex See, Lap Chan
  • Patent number: 6764914
    Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: July 20, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Alex See, Cher Liang Randall Cha, Shyue Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong, Jun Song, Chua Chee Tee
  • Publication number: 20040137721
    Abstract: An improved and new process for fabricating self-aligned metal barriers by atomic layer deposition, ALD, capable of producing extremely thin, uniform, and conformal metal barrier films, selectively depositing on copper, not on silicon dioxide interlevel dielectric, in multi-layer dual damascene trench/via processing. Silicon nitride is presently used as a insulating copper barrier. However, silicon nitride has a relatively high dielectric constraint, which deteriorates ICs with increased RC delay. Copper metal barriers of niobium and tantalum have been deposited by atomic layer deposition on copper. With high deposition selectivity, the barrier metal is only deposited over copper, not on silicon dioxide, which eliminates the need of an insulating barrier of silicon nitride.
    Type: Application
    Filed: January 9, 2003
    Publication date: July 15, 2004
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Boon Kiat Lim, Alex See