Patents by Inventor Alex See

Alex See has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9287197
    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 15, 2016
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Benfu Lin, Hong Yu, Lup San Leong, Alex See, Wei Lu
  • Patent number: 9242341
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Benfu Lin, Wei Lu, Alex See
  • Patent number: 9242338
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Benfu Lin, Lei Wang, Xuesong Rao, Wei Lu, Alex See
  • Patent number: 9209275
    Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes removing a central plug from between a first memory cell and a second memory cell to define a center gap. Each of the first and second memory cells include a control gate with a control gate height, a cap overlying the control gate, a select gate adjacent to the control gate, and a select gate dielectric between the control gate and the select gate. The select gate is recessed to a select gate height while the cap overlies the control gate, where the select gate height is less than the control gate height. A memory spacer is formed overlying the select gate dielectric and adjacent to the control gate.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zheng Zou, Alex See
  • Patent number: 9202746
    Abstract: Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: December 1, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lei Wang, Lup San Leong, Wei Lu, Alex See
  • Publication number: 20150311221
    Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 29, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jingyan Huang, Chuan Wang, Chim Seng Seet, Yun Ling Tan, Alex See
  • Publication number: 20150303068
    Abstract: Methods of forming a semiconductor device are presented. The method includes providing a wafer with top and bottom wafer surfaces. The wafer includes edge and non-edge regions. A dielectric layer having a desired concave top surface is provided on the top wafer surface. The method includes planarizing the dielectric layer to form a planar top surface of the dielectric layer. The desired concave top surface of the dielectric layer thicknesses compensates for different planarizing rates at the edge and non-edge regions of the wafer.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 22, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lei WANG, Xuesong RAO, Wei LU, Alex SEE
  • Publication number: 20150279743
    Abstract: Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Liang LI, Xuesong RAO, Martina DAMAYANTI, Wei LU, Alex SEE, Yoke Leng LIM
  • Publication number: 20150187641
    Abstract: Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 2, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lei Wang, Lup San Leong, Wei Lu, Alex See
  • Patent number: 9023725
    Abstract: A device and methods for forming the device are disclosed. The method includes providing a substrate. A gate having a gate electrode and sidewall spacers are formed adjacent to sidewalls of the gate. A height HG of the gate is lower than a height HS of the sidewall spacers. A metal or metal alloy layer is deposited over the spacers, gate and the substrate. The substrate is processed to form metal silicide contact at least over the gate electrode. A top surface of the metal silicide contact over the gate electrode is about coplanar with a top of the sidewall spacer, and the difference between the height of the gate and spacers prevent formation of metal silicide filaments on top of the sidewall spacers.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 5, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Kwee Liang Yeo, Chim Seng Seet, Zheng Zou, Alex See
  • Publication number: 20150111467
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 23, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Benfu LIN, Wei LU, Alex SEE
  • Publication number: 20150111469
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 23, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Benfu LIN, Lei WANG, Xuesong RAO, Wei LU, Alex SEE
  • Publication number: 20140374920
    Abstract: A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.
    Type: Application
    Filed: September 11, 2014
    Publication date: December 25, 2014
    Inventors: Zheng ZOU, Alex SEE, Huang LIU, Hai CONG
  • Patent number: 8852968
    Abstract: Methods of deducing oxide thickness using calculated and measured scattering spectra are provided. Embodiments include depositing an oxide over a semiconductor wafer, reducing the oxide from a portion of the semiconductor wafer, and deducing a thickness of oxide remaining at a location within the portion using scatterometric metrology. Embodiments further include deducing the thickness by: calculating scattering spectra for a plurality of oxide thicknesses, producing calculated scattering spectra, monitoring scattering spectra at the location within the portion of the semiconductor wafer, comparing the monitored scattering spectra at the location to the calculated scattering spectra, determining a closest matching calculated scattering spectra to the monitored scattering spectra at the location, and obtaining an oxide thickness corresponding to the closest matching calculated scattering spectra.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Liang Li, Zheng Zou, Huang Liu, Alex See
  • Publication number: 20140264911
    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Globalfoundries Singapore Pte. Ltd.
    Inventors: Benfu LIN, Hong Yu, Lup San, Alex See, Wei Lu
  • Patent number: 8836139
    Abstract: A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: September 16, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zheng Zou, Alex See, Huang Liu, Hai Cong
  • Patent number: 8828858
    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
  • Publication number: 20140234993
    Abstract: Methods of deducing oxide thickness using calculated and measured scattering spectra are provided. Embodiments include depositing an oxide over a semiconductor wafer, reducing the oxide from a portion of the semiconductor wafer, and deducing a thickness of oxide remaining at a location within the portion using scatterometric metrology. Embodiments further include deducing the thickness by: calculating scattering spectra for a plurality of oxide thicknesses, producing calculated scattering spectra, monitoring scattering spectra at the location within the portion of the semiconductor wafer, comparing the monitored scattering spectra at the location to the calculated scattering spectra, determining a closest matching calculated scattering spectra to the monitored scattering spectra at the location, and obtaining an oxide thickness corresponding to the closest matching calculated scattering spectra.
    Type: Application
    Filed: February 15, 2013
    Publication date: August 21, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Liang LI, Zheng ZOU, Huang LIU, Alex SEE
  • Patent number: 8766454
    Abstract: An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: July 1, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Wang Ling Goh
  • Publication number: 20140167121
    Abstract: A device and methods for forming the device are disclosed. The method includes providing a substrate. A gate having a gate electrode and sidewall spacers are formed adjacent to sidewalls of the gate. A height HG of the gate is lower than a height HS of the sidewall spacers. A metal or metal alloy layer is deposited over the spacers, gate and the substrate. The substrate is processed to form metal silicide contact at least over the gate electrode. A top surface of the metal silicide contact over the gate electrode is about coplanar with a top of the sidewall spacer, and the difference between the height of the gate and spacers prevent formation of metal silicide filaments on top of the sidewall spacers.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Kwee Liang YEO, Chim Seng SEET, Zheng ZOU, Alex SEE