Patents by Inventor Alex See

Alex See has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030069151
    Abstract: A method of preparing a silicon surface for a subsequent processing said such as thermal oxidation, or metal silicide formation, via use of a novel wet chemical clean procedure, has been developed. The novel wet chemical clean procedure is comprised of three specific stages, with the first stage featuring the removal of organic contaminants and the growth of a native oxide layer on the silicon surface. A second stage features removal of the native oxide layer and removal of metallic contaminants from the silicon surface, while the third stage is used to dry the silicon surface. The novel wet chemical clean procedure is performed in less time, and using less chemicals, then counterpart wet chemical cleans also used for the preparation of silicon surfaces for subsequent processing steps.
    Type: Application
    Filed: October 9, 2001
    Publication date: April 10, 2003
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jianhui Ye, Simon Chooi, Alex See
  • Patent number: 6518133
    Abstract: A method of manufacturing a transistor with a small self aligned gate and self aligned elevated source/drain regions. A first insulating layer is formed over a substrate. A first opening is formed in the first insulating layer to expose the substrate. We form a gate dielectric layer over the substrate in the first opening. Next, first spacers are formed on the sidewalls of the first insulating layer. A gate layer is formed over the first insulating layer, the first spacers, and the gate dielectric layer. We planarize the gate layer to form a gate electrode. The first spacers are removed to form LDD openings. Next, we form lightly doped source/drain regions in the substrate in the LDD openings. Subsequently, second spacers are formed on the sidewalls of the first insulating layer and on the sidewalls of the gate electrode to form S/D openings. Source/drain regions are formed in the substrate in the S/D openings. Next, we form a conductive layer over the substrate at least partially filling the S/D openings.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: February 11, 2003
    Assignee: Chartered Semiconductor Manufacturing LTD
    Inventors: Alex See, Yeow Kheng Lim, Cher Liang Randall Cha
  • Patent number: 6492242
    Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures.
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: December 10, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Alex See, Cher Liang Randall Cha, Shyuz Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong, Jun Song, Chua Chee Tee
  • Patent number: 6475875
    Abstract: A process for forming insulator filled, shallow trench isolation (STI), regions in a semiconductor substrate, featuring a disposable polysilicon stop layer used to allow uniform insulator fill to be obtained, independent of shallow trench width, has been developed. The process features filling shallow trench shapes with a first high density plasma (HDP), deposited silicon oxide layer, followed by the deposition of the thin polysilicon stop layer, and a second HDP silicon oxide layer. After a planarizing chemical mechanical polishing procedure residual regions of the second HDP silicon oxide, still remaining in regions overlying the insulator filled shallow trench shapes, are selectively removed using the thin polysilicon layer as a stop layer. The polysilicon layer is then thermally oxidized. The thickness of the polysilicon layer can be varied such that the resultant polysilicon oxide layer serves to alleviate the possible oxide loss in the STI regions during subsequent clean processes.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: November 5, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Pang Chong Hau, Chen Feng, Alex See, Peter Hing
  • Patent number: 6472697
    Abstract: A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: October 29, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Wang Ling Goh, Victor Seng Keong Lim
  • Publication number: 20020155703
    Abstract: A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.
    Type: Application
    Filed: April 20, 2001
    Publication date: October 24, 2002
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Shaoyin Chen, Ze Xiang Shen, Alex See, Lap Chan
  • Patent number: 6468880
    Abstract: A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: October 22, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Tae Jong Lee, Wang Ling Goh
  • Publication number: 20020132448
    Abstract: A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.
    Type: Application
    Filed: March 14, 2001
    Publication date: September 19, 2002
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yeow Kheng Lim, Randall Cher Laing Cha, Alex See, Tae Jong Lee, Wang Ling Goh
  • Publication number: 20020127834
    Abstract: A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug.
    Type: Application
    Filed: May 8, 2002
    Publication date: September 12, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Wang Ling Goh, Victor Seng Keong Lim
  • Publication number: 20020127816
    Abstract: A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.
    Type: Application
    Filed: March 1, 2001
    Publication date: September 12, 2002
    Inventors: Randall Cher Liang Cha, Yeow Kheng Lim, Alex See, Tae Jong Lee, Wang Ling Goh
  • Patent number: 6436833
    Abstract: A method of forming shallow trench isolations is described. An etch stop layer is deposited on the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the etch stop layer into the semiconductor substrate to separate active areas. An oxide layer is deposited over the etch stop layer and within the isolation trenches wherein the oxide fills the isolation trenches and overlies the etch stop layer on the active areas. A polysilicon layer is deposited overlying the oxide layer within the isolation trenches and the oxide layer overlying the etch stop layer. The polysilicon layer is polished away until the oxide layer overlying the etch stop layer is exposed and the polysilicon layer remains only overlying the oxide layer in the isolation trenches. The polysilicon layer is oxidized whereby the oxidized polysilicon layer has a height close to the height of the oxide layer overlying the etch stop layer.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: August 20, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chong Hau Pang, Chen Feng, Alex See, Peter Hing
  • Patent number: 6432797
    Abstract: A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: August 13, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Randall Cher Liang Cha, Tae Jong Lee, Alex See, Lap Chan, Yeow Kheng Lim
  • Publication number: 20020102802
    Abstract: A method for forming a thicker silicide over a MOS device is described. This is achieved using a process where the gate structure is formed by conventional techniques upon a substrate. A low-energy implantation is performed to form lightly doped source and drain (LDD) regions in the substrate in the areas not protected by the gate structure. A first spacer composed of tetraethyl-oxysilane (TEOS oxide), for example, is formed along the sidewalls of the gate structure. A second low-energy implantation is performed to form the source and drain (S/D) in the areas not protected by the gate structure and first spacer. A layer of metal such as titanium (Ti), for example, is then deposited over the surface of the gate structure. A second sidewall spacer composed of titanium nitride (TiN), for example, is formed along the sidewalls of the gate structure covering the metal over the first sidewall spacer. A layer of polysilicon is then deposited over the surface of the gate structure.
    Type: Application
    Filed: February 1, 2001
    Publication date: August 1, 2002
    Inventors: Cheng Cheh Tan, Randall Cher Liang Cha, Alex See, Lap Chan
  • Publication number: 20020098689
    Abstract: A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 25, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Yung Fu Chong, Kin Leong Pey, Alex See
  • Publication number: 20020098661
    Abstract: A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench.
    Type: Application
    Filed: January 25, 2001
    Publication date: July 25, 2002
    Inventors: Randall Cher Liang Cha, Tae Jong Lee, Alex See, Lap Chan, Yeow Kheng Lim
  • Publication number: 20020094622
    Abstract: A method for forming a self-aligned, recessed channel, MOSFET device that alleviates the problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A substrate with an active area encompassed by a shallow trench isolation (STI) region is provided. A mask oxide layer is then patterned and etched to expose the substrate and a portion of the STI region. The surface is etched and the mask oxide layer is eroded away while creating a gate recess in the unmasked area. A thin pad oxide layer is then grown overlying the surface followed by a deposition of a thick silicon nitride layer covering the surface and filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown causing the pad oxide layer to thicken. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown causing the pad oxide layer to further thicken.
    Type: Application
    Filed: February 5, 2002
    Publication date: July 18, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Sneedharan Pillai Sneelal, Francis Yong Wee Poh, James Yong Meng Lee, Alex See, C.K. Lau, Ganesh Shankar Samudra
  • Patent number: 6406975
    Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: June 18, 2002
    Assignee: Chartered Semiconductor Manufacturing Inc.
    Inventors: Victor Seng Keong Lim, Young-Way Teh, Ting-Cheong Ang, Alex See, Yong Kong Siew
  • Patent number: 6399471
    Abstract: A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: June 4, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Wang Ling Goh, Victor Seng Keong Lim
  • Publication number: 20020064918
    Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature.
    Type: Application
    Filed: November 29, 2000
    Publication date: May 30, 2002
    Inventors: Pooi See Lee, Kin Leong Pey, Alex See, Lap Chan
  • Patent number: 6391731
    Abstract: A new method of forming MOS transistors with shallow source and drain extensions and deep source and drain junctions in the manufacture of an integrated circuit device has been achieved. Gates are provided overlying a semiconductor substrate. Temporary sidewall spacers are formed on the gates. Ions are implanted into the exposed semiconductor substrate to form a deep amorphous layer. Ions are implanted into the deep amorphous layer to form pre-annealed source and drain junctions. The temporary sidewall spacers are removed. Ions are implanted into the exposed semiconductor substrate to form a shallow amorphous layer. Ions are implanted into the shallow amorphous layer to form pre-annealed source and drain extensions. A capping layer may be deposited overlying the semiconductor substrate and the gates to protect the semiconductor substrate during irradiation.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: May 21, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yung Fu Chong, Kin Leong Pey, Alex See