Abstract: In one aspect, a system may receive, via a user graphical user interface, a request to perform a data migration from a source data center to a destination data center. A system may in response to receiving the request, perform the data migration by: (1) creating a copy of a tenants structure that lists information about each tenant of the source data center, wherein a respective tenant is a representation of a user on a platform level, (2) creating and activating, on the destination data center, a plurality of new user accounts that match a main login body and suffix of a plurality of existing user accounts on the source data center, (3) re-registering, at the destination data center, agents from the source data center; and (4) migrating backup data from the source data center to the destination data center.

Abstract: An integrated circuit includes a clock macro circuit. The clock macro circuit includes first, second, and third latch circuits and a multiplexer circuit. The first latch circuit is coupled to the second latch circuit. The multiplexer circuit is coupled to the second and third latch circuits. The clock macro circuit includes programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second latch circuit, the third latch circuit, and the multiplexer circuit. Programming the programmable vias causes the clock macro circuit to function as a selected type of clock circuit.

Abstract: Disclosed herein are systems and method for providing nested frontend applications in a user interface of a management application. An exemplary method may include: generating a graphical user interface (GUI) for the management application, wherein the GUI includes a first extension point that includes a plurality of extensions, wherein each extension of the plurality of extensions is a standalone frontend application; injecting, during runtime of the management application, a first extension into the first extension point based on a personal configuration file, wherein the first extension is included in the plurality of extensions after injection; in response to receiving, via the GUI, a selection of the first extension, generating, on the GUI, a second extension point corresponding to the first extension, wherein the second extension point includes an additional plurality of extensions; and injecting, during the runtime, a second extension into the second extension point.

Abstract: Disclosed herein are systems and method for providing nested frontend applications in a user interface of a management application. An exemplary method may include: generating a graphical user interface (GUI) for the management application, wherein the GUI includes a first extension point that includes a plurality of extensions, wherein each extension of the plurality of extensions is a standalone frontend application; injecting, during runtime of the management application, a first extension into the first extension point based on a personal configuration file, wherein the first extension is included in the plurality of extensions after injection; in response to receiving, via the GUI, a selection of the first extension, generating, on the GUI, a second extension point corresponding to the first extension, wherein the second extension point includes an additional plurality of extensions; and injecting, during the runtime, a second extension into the second extension point.

Abstract: Disclosed herein are systems and method for multiplexing data of an underlying index. In an exemplary aspect, an index handler may: search for a data file in a plurality of data buckets associated with an index, wherein at least one respective data bucket of a plurality of data buckets is attached to a respective slot of a plurality of slots; identify, based on the searching, a first data bucket of the plurality of data buckets that comprises the data file; in response to determining that the first data bucket is not attached to any of the plurality of slots, attach the first data bucket to a first slot of the plurality of slots; and enable access to the data file via the first data bucket attached to the first slot.

Abstract: Mitochondrially targeted antioxidants are used to prevent and treat severe inflammatory conditions including viral infection (such as COVID-19), systemic shock, trauma, burns, surgery associated with significant tissue damage, toxic damage, and damage associated with autoimmune reactions.

Abstract: Disclosed herein are systems and method for multiplexing data of an underlying index. In an exemplary aspect, an index handler may: search for a data file in a plurality of data buckets associated with an index, wherein at least one respective data bucket of a plurality of data buckets is attached to a respective slot of a plurality of slots; identify, based on the searching, a first data bucket of the plurality of data buckets that comprises the data file; in response to determining that the first data bucket is not attached to any of the plurality of slots, attach the first data bucket to a first slot of the plurality of slots; and enable access to the data file via the first data bucket attached to the first slot.

Abstract: Disclosed herein are systems and method for multiplexing data of an underlying index. In an exemplary aspect, an index handler may generate a plurality of slots and a plurality of data buckets for a traditional index. The index handler may receive, from a software application, a request to access a data file. The index handler may determine whether any slot of the plurality of slots is attached to a respective data bucket of the plurality of data buckets comprising the data file. In response to determining that a first slot of the plurality of slots is attached to a first data bucket comprising the data file, the index handler may enable, via the first data bucket attached to the first slot, access to the data file to the software application.

Abstract: A circuit design system is configured to generate a circuit design for an integrated circuit. The circuit design system includes a placement tool configured to generate a graph comprising flows between objects in a first level of a pyramid and targets in the first level. The placement tool generates clusters of objects in a second level of the pyramid in each of the objects in the first level. The objects in the first and the second levels comprise circuit blocks in the circuit design. The placement tool generates clusters of targets in the second level of the pyramid in each of the targets in the first level. The targets in the first and the second levels include subregions of the integrated circuit. The placement tool generates flows from the objects in the second level to the targets in the second level for a placement of the circuit blocks.

Abstract: An integrated circuit includes first and second routing crossbars. The second routing crossbar includes first conductors routed in a first direction in a first conductive layer and second conductors routed in a second direction that is perpendicular to the first direction in a second conductive layer. A first subset of the first conductors is coupled to the first routing crossbar. The first subset of the first conductors is coupled to a second subset of the first conductors through a first subset of the second conductors that is coupled to the first and second subsets of the first conductors through first vias. The second subset of the first conductors is coupled to a second subset of the second conductors to through second vias. At least one of the first conductors is decoupled from another one of the first conductors by third vias.

Abstract: An integrated circuit includes a clock macro circuit. The clock macro circuit includes first, second, and third latch circuits and a multiplexer circuit. The first latch circuit is coupled to the second latch circuit. The multiplexer circuit is coupled to the second and third latch circuits. The clock macro circuit includes programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second latch circuit, the third latch circuit, and the multiplexer circuit. Programming the programmable vias causes the clock macro circuit to function as a selected type of clock circuit.

Abstract: Disclosed herein are systems and method for multiplexing data of an underlying index. In an exemplary aspect, an index handler may generate a plurality of slots and a plurality of data buckets for a traditional index. The index handler may receive, from a software application, a request to access a data file. The index handler may determine whether any slot of the plurality of slots is attached to a respective data bucket of the plurality of data buckets comprising the data file. In response to determining that a first slot of the plurality of slots is attached to a first data bucket comprising the data file, the index handler may enable, via the first data bucket attached to the first slot, access to the data file to the software application.

Abstract: An integrated circuit may include a multi-layer structure having alternating metal interconnection layers and via layers superimposed on a base layer having electronic components, functional blocks, or both. At least two of the via layers may be customizable and may be used to form customized interconnections that may customize functionality of the resulting integrated circuit. In a variant, at least some of the layers may have a default structure that may result in a default integrated circuit functionality; the default structure may be changed to customize functionality. One or more metal interconnection layers may also be customizable. Additionally, transistors of the base layer may be customized for speed and/or power consumption by adjusting voltage thresholds and/or gate lengths.

Abstract: A low-density parity check min-sum decoder including a variable node processing unit having N+1 inputs. A first bank of N+1 two-input adders each have an associated output, and at least one of the N+1 inputs go to more than two of the adders of the first bank. A second bank of N two-input adders has no adders in common with the first bank. At least one of the adders of the first bank provides its associated output to more than one adder of the second bank. The banks of adders are disposed in series. A sign module outputs a sign value produced from one of the inputs and an output from one of the adders of the second bank. N+1 outputs are provided, where one of the outputs is the sign value.

Abstract: A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

Abstract: A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.

Abstract: A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.

Abstract: A network-fabric used for testing with an external or internal tester is shown for a Structured ASIC. In one embodiment, the Structured ASIC uses a microprocessor, network-aware IO routing fabric comprising network agents in a scalable novel configuration, with the network-aware IO having a plurality of blocks connected in series in a plurality of paths in the fabric leading to and from the microprocessor and memory and/or logic, the blocks acting as intelligent network agents under processor control to determine what state they can assume, whether to pass a data signal or not along these paths, comprising open loops and closed loops running to and from the microprocessor and memory and/or logic, primarily for testing and determining the state of the memory and logic. In another embodiment a JTAG controller may receive JTAG test commands from an external testing apparatus and set up to communicate along the fabric.

Abstract: A clock architecture for a Structured ASIC chip, manufactured using a CMOS process is shown. A via-configurable logic block (VCLB) architecture in the Structured ASIC has a core region containing memory and logic cells arranged in columns that are supplied by a clock network having a global clock network tree and a low-level clock mesh to distribute the global clock signal in a repeating pattern. The clock mesh has a fishbone configuration in outline and allows for scalable expansion of the clock network. In one embodiment 36 global clocks may be provided to the Structured ASIC, with four clocks per logic cell. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node, having several metal layers but preferably is programmable on a single via layer.

Abstract: A low-density parity check min-sum decoder including a variable node processing unit having N+1 inputs. A first bank of N+1 two-input adders each have an associated output, and at least one of the N+1 inputs go to more than two of the adders of the first bank. A second bank of N two-input adders has no adders in common with the first bank. At least one of the adders of the first bank provides its associated output to more than one adder of the second bank. The banks of adders are disposed in series. A sign module outputs a sign value produced from one of the inputs and an output from one of the adders of the second bank. N+1 outputs are provided, where one of the outputs is the sign value.