Abstract: A method for transforming a customer's memory design into an RRAM memory design. A port mapping table is created that lists the ports of the customer memories, and an instance types table is created that lists the customer memories. For each customer memory that is listed in the instance types table, any virtual buffer nets are removed, and any virtual buffers are removed. Any loose nets so created are reconnected to an RRAM cell in the RRAM memory design. The customer memory instance are then removed. A constraints file is updated from customer memory port designations to RRAM port designations. Automated test logic is inserted into the RRAM memory design, layout on the RRAM memory design is performed, and timing constraints on the RRAM memory design are satisfied. A modified version of the RRAM memory design is returned to the customer for verification. The modified version is made using the port mapping table.

Abstract: The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. In an exemplary aspect of the present invention, a method for outputting a sequence of commands and data described by a flowchart includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A module (e.g., a CKD, or the like) is generated to include the ROM, wherein the module receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.

Abstract: A user-defined memory design is mapped to memories of a base platform for an IC that contains a plurality of memory sets, each containing a plurality of memories of a predetermined type. An optimal memory set is selected from the plurality of memory sets for the design by selecting a preference rate for each memory set from the plurality of sets based on the design and its connections to portions of the IC, and selectively assigning the design to one of the memory sets based on the preference rate. The design is optimally mapped to a plurality of memories of the selected memory set by defining an index of the position of each customer memory in the selected memory set. The customer memories in the selected memory set are arranged in an order, and successive numbers of memories of the selected memory set are assigned to each customer memory in order.

Abstract: A plurality of user-defined memories are mapped to pre-defined basic memories, such as defined on a base platform. The user-defined memories are dividing into classes of similar memories. A mapping technique is selected for members of a selected class of user-defined memories that minimizes the ratio (maxi,j(USEDi,j/AVAILi,j)) of basic memories that have been mapped to basic memories that are available for mapping. If the number of different memory mappings is smaller than a threshold the mapping technique is applied to each user-defined memory. If the number of different memory mappings is greater than the threshold, the groups are arranged in ordered queues of single memory types based on a mapping price and the mapping technique is selected based on a memory of each group and is applied to each user-defined memory in the respective group.

Abstract: Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. T coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.

Abstract: A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present invention may simplify the functional steps used in the high-level description to define the logic function and thus create a logic circuit with an optimized number of AND/OR switches.

Abstract: Objects are placed in a rectangle and their coordinates of the objects and are adjusted to establish a substantially uniform density of objects in the rectangle. The evaluation of coordinates is performed by placing the wires between cells coordinates and adjusting the cell coordinates to connect the cells to the wires. The substantially uniform density is achieved by dividing the rectangle into first and second rectangles having equal free areas and into third and fourth rectangles having equal areas of objects. The coordinates of the objects are adjusted based on boundaries between the first and second rectangles and between the third and fourth rectangles.

Abstract: The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.

Abstract: Objects are assigned to points in a rectangle by dividing the rectangle is divided into a plurality of smaller rectangles and applying an object assignment procedure, such as Kuhn's algorithm, to initially assigned objects in each second rectangle. The initial assignment is performed by calculating a maximal cost of assignment of objects to points, and selecting an assignment of objects having a minimum value of maximal cost, identified by iteratively recalculating the maximal matching assignment based on a midpoint of between the minimum and maximum costs.

Abstract: The present invention is directed to a parallel processor language, a method for translating C++ programs into a parallel processor language, and a method for optimizing execution time of a parallel processor program. In an exemplary aspect of the present invention, a parallel processor program for defining a processor integrated circuit includes a plurality of processor commands with addresses. The plurality of processor commands may includes a starting processor command, and each of the plurality of processor commands includes one or more subcommands. When the processor integrated circuit executes the parallel processor program, the processor integrated circuit executes the staring processor command first and then executes the rest of the plurality of processor commands based on an order of the addresses.

Abstract: The present invention is directed to a method and apparatus for mapping a customer memory onto a plurality of physical memories.

Abstract: A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number which establishes a de-serialization level for frequency reduction or phase shifting. An output provide an output data stream at the desired output frequency.

Abstract: A routing multiplexer system provide p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.

Abstract: An original netlist is transformed to one employing universal gates. A negation net is created for each net coupled to an input or output of each gate and an input of each inverter in the original net. Each gate is removed from the original netlist and a universal gate is inserted so that the nets previously coupled to the inputs and output of the removed gate and a negation of those nets are coupled to the inputs and outputs of the inserted universal gate in a selected arrangement. Each inverter is removed from the original netlist and the net previously coupled to the input of the inverter is negated. A universal gate comprises gates performing anding and oring functions whose inputs and outputs are selectively coupled to the nets of the original netlist, and their negations.

Abstract: The present invention is directed to a method and apparatus of IC implementation based on a C++ language description. In an exemplary aspect of the present invention, a method for evaluating a C++ description by an IC includes the following steps. First, a C++ description including a C++ program is provided. Then, the C++ program is stored in a first memory module (e.g., a ROM, or the like) of an IC. Next, a scalar input and/or an input array may be provided to the IC. Then, the C++ program may be executed by a control device module of the IC. Next, a scalar output and/or an output array may be read from the IC.

Abstract: The present invention is a method and apparatus for optimizing the design of a combinational circuit. The method includes constructing a circuit sheaf for the combinational circuit and then performing vector optimization with domination. In the preferred embodiment, a complete BDD B is determined and, from that, a list of F-sets is computed. If the combinational circuit includes cells other than NOT, AND and XOR cells, the circuit is first transformed such that it only has those types of cells.

Abstract: Constant pins are determined in a combinational circuit by associating an input of a combinational circuit with a first variable and a second variable, with the second variable being the complement of the first variable. For a first logical cell interconnected to such input, a first mathematical representation and a second mathematical representation are computed. The first mathematical representation is a function of the operation of the first logical cell and a function of the first variable, and the second mathematical representation is a function of the operation of the first logical cell and a function of the second variable. A determination is then made as to whether one of the first and second mathematical representations is equal to a constant.

Abstract: The present invention involves a method for determining constant pins in a combinational circuit. The method comprises the steps of associating an input of a combinational circuit with a first variable and a second variable, wherein said second variable is the compliment of said first variable, computing for a first logical cell interconnected to said input a first canonical representation, wherein said first canonical representation is a function of the operation of said first logical cell and a function of said first value, computing for said first logical cell a second canonical representation, wherein said second canonical representation is a function of the operation of said first logical cell and a function of said second value, determining whether one of said first and second canonical representations is equal to zero.

Abstract: The present invention involves a method for reducing delay of a net. The method includes constructing a time-space grid, said time-space grid corresponding to a net, passing a wave through the time-space grid, said wave having a wave value, and inserting a buffer at a point on said time-space grid where insertion of the buffer increases a wave value. The buffer can be a negative buffer or positive buffer. Generally, a second wave is passed through the time-space grid simultaneously with the first wave. Typically, the second wave and the first wave are inverted.

Abstract: The invention is directed to optimization of an initial routing that connects nets on a surface, each of the nets including plural interconnected net pins. The surface is divided into a set of areas, and a boundary pin is defined at each point on a boundary of one of the areas where the boundary of the one of the areas intersects a net. Routing optimization is then performed in at least one of the areas, the routing optimization optimizing the routing among the net pins and the boundary pins within the at least one of the areas. The invention is also directed to optimization of an initial routing that connects nets on a surface, each of the nets including plural interconnected net pins. The surface is divided into a first set of pre-defined areas, and routing optimization is performed independently in each of the pre-defined areas in the first set.