Patents by Inventor Alexander Barr

Alexander Barr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200242495
    Abstract: Providing updated build parameters to an additive manufacturing machine to improve quality of a part manufactured by the machine. Sensor data is received from the additive manufacturing machine during manufacture of the part using a first set of build parameters. The first set of build parameters is received. An evaluation parameter is determined based on the first set of build parameters and the received sensor data. Thermal data is generated based on a thermal model of the part derived from the first set of build parameters. A first algorithm is applied to the received sensor data, the determined evaluation parameter, and the generated thermal data to produce a second set of build parameters, the first algorithm being trained to improve the evaluation parameter. The second set of build parameters is output to the additive manufacturing machine to produce a second part.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 30, 2020
    Inventors: Subhrajit ROYCHOWDHURY, Alexander CHEN, Xiaohu PING, Justin GAMBONE, JR., Thomas CITRINITI, Brian BARR
  • Patent number: 10586865
    Abstract: A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 10, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Scott Warrick, Justin Dougherty, Alexander Barr, Christian Larsen, Marc L. Tarabbia, Ying Ying
  • Publication number: 20190103490
    Abstract: A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Scott WARRICK, Justin DOUGHERTY, Alexander BARR, Christian LARSEN, Marc L. TARABBIA, Ying YING
  • Publication number: 20180169815
    Abstract: A powered high-speed cutting tool that also locates objects behind sheet material and subsequently cuts around the object. The tool incorporates at least one sensor having a transceiver emitting a signal to detect at least one from the group of object density, conductivity, distance, and identification. The sensor is housed within a sensor unit that is part of the body of the cutting tool. The sensor unit can be incorporated into the body or removable from the cutting tool. A marking unit is used to mark the cutting area of the sheet material and is generally part of or located near a sensor unit. Indicator members, such as lights, audio, and/or display screen, are used to provide information to the user.
    Type: Application
    Filed: February 15, 2018
    Publication date: June 21, 2018
    Inventors: William Alexander Barr, Deborah Fulton Barr, William Harrison Fulton
  • Publication number: 20170113316
    Abstract: A powered high-speed cutting tool that also locates objects behind sheet material and subsequently cuts around the object. The tool incorporates at least one sensor having a transceiver emitting a signal to detect at least one from the group of object density, conductivity, distance, and identification. The sensor is housed within a sensor unit that is part of the body of the cutting tool. The sensor unit can be incorporated into the body or removable from the cutting tool. A marking unit is used to mark the cutting area of the sheet material and is generally part of or located near a sensor unit. Indicator members, such as lights, audio, and/or display screen, are used to provide information to the user.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 27, 2017
    Inventors: William Alexander Barr, Deborah Fulton Barr, William Harrison Fulton
  • Publication number: 20110311328
    Abstract: A powered cutting tool for locating objects behind sheet material and subsequently cutting around the object. The tool incorporates at least one sensor having a transceiver emitting signal to detect at least one from the group of object density, conductivity, depth, and identification. The sensor is housed within a sensor unit that is affixed to the body of the cutting tool. The sensor unit can be integral with, or removable from, the cutting tool. A marking unit is used to mark the cutting area of the sheet material and is generally integral with, or located near, a sensor unit. Indicator members, such as lights, audio, and/or display screen, are used to provide information to the user.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 22, 2011
    Inventors: William Alexander Barr, Deborah Fulton Barr, William Harrison Fulton
  • Patent number: 7763596
    Abstract: This invention is directed to a method for treating an inflammatory condition, treating haematological and other malignancies, causing immunosuppression, or preventing or treating transplant rejection in man or other animals which comprises administering to a patient a compound that has the structure of Formula (I) or Formula (II) as defined below, or a pharmaceutically acceptable derivative thereof or pro-drug therefor, wherein R?NH2, NHR1, NHOR2, NHNHR2, NHCOR2, and R1?C(1-4)alkyl, C(3-6)cycloalkyl, Cn, where n=1-3, R2=methyl, ethyl, R3=alkyl, cycloalkyl, substituted alkyl, substituted cycloalkyl, aryl, heteroaryl, substituted aryl, or substituted hetrecoaryl; wherein R4, R5?C(1-4)alkyl. Novel compounds according to Formula (III), wherein R6 and R7 are any of H, CH3CO, CH3CH2CO, CH3CH2CH2CO provided that R6 and R7 are not both H, or Formula (IV), wherein R8 and R9 are any of H, CH3CO, CH3CH2CO or CH3CH2CH2CO, having use in such methods, are also described.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: July 27, 2010
    Assignee: The University of Manchester
    Inventors: Stephen Alexander Barr, Michael Anthony McKervey, Hughes Jean-Pierre Miel, David William Ray, Andrew Michael Brass
  • Publication number: 20070235807
    Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
    Type: Application
    Filed: May 1, 2007
    Publication date: October 11, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Ted White, Alexander Barr, Bich-Yen Nguyen, Marius Orlowski, Mariam Sadaka, Voon-Yew Thean
  • Publication number: 20070197095
    Abstract: An electrical connector assembly includes an organizer plate having a plurality apertures for receiving termination devices. Each termination device includes a shield box, an insulator, and a socket contact. The shield box has at least one outwardly extending ground contact element and a latch member. When the termination device is inserted into an aperture of the organizer plate, the latch member on the shield box engages a surface of the organizer plate to prevent withdrawal of the termination device.
    Type: Application
    Filed: January 25, 2007
    Publication date: August 23, 2007
    Inventors: Steven Feldman, Kevin Meredith, Rudy Densmore, Joseph Castiglione, Alexander Mathews, Alexander Barr, Richard Scherer
  • Publication number: 20070136031
    Abstract: The present invention includes a method of electronically designing an article, including accessing an electronic article design system, selecting an article type to design, and iteratively configuring a group of characteristics by selecting one or more options for each characteristic and/or iteratively modeling the article performance based on a selection of one or more performance parameters for each performance model. In the iterative configuration and modeling step, the electronic article design system automatically presents the characteristics and the performance models based on the article type selected, dynamically updates the article for each step of the iterative configuration and/or modeled performance, and automatically resolves conflicts between iteratively configured characteristics, between iteratively modeled performances, and across iteratively configured characteristics and modeled performances.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 14, 2007
    Inventors: Steven Feldman, Jason Randall, Alexander Barr, Abhay Joshi
  • Publication number: 20070082453
    Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
    Type: Application
    Filed: December 12, 2006
    Publication date: April 12, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Marius Orlowski, Alexander Barr, Mariam Sadaka, Ted White
  • Publication number: 20060292898
    Abstract: An electrical interconnection system includes a printed circuit board having a receiving cavity therein. At least one circuit trace is located on a side wall of the cavity. An electrical connector is configured for insertion into the receiving cavity. The electrical connector has an electrical contact positioned to contact the at least one circuit trace when inserted into the receiving cavity.
    Type: Application
    Filed: June 23, 2005
    Publication date: December 28, 2006
    Inventors: Kevin Meredith, Alexander Barr, Steven Feldman
  • Publication number: 20060240697
    Abstract: A connector assembly includes a frame mounted on a printed circuit substrate having a plurality of contact pads, and a spring member configured for insertion into the frame. The spring member has a flexible circuit supported thereon. The spring member and frame are shaped to exert biasing forces in two non-parallel directions when the spring member is inserted into the frame.
    Type: Application
    Filed: April 26, 2005
    Publication date: October 26, 2006
    Inventors: Daniel Cronch, Alexander Barr, Wing Chow, Steven Feldman, Richard Scherer
  • Publication number: 20060228851
    Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 12, 2006
    Inventors: Mariam Sadaka, Alexander Barr, Dejan Jovanovic, Bich-Yen Nguyen, Voon-Yew Thean, Shawn Thomas, Ted White
  • Publication number: 20060174463
    Abstract: One aspect provides a capacitor feedthrough assembly having an electrically conductive member dimensioned to extend at least partially through a feedthrough hole of a case of the capacitor, the conductive member having a passage therethrough.
    Type: Application
    Filed: March 29, 2006
    Publication date: August 10, 2006
    Inventors: Michael O'Phelan, Brian Schmidt, James Poplett, Robert Tong, Richard Kavanagh, Rajesh Iyer, Alexander Barr, Luke Christenson, Brian Waytashek, Brian Schenk, Gregory Sherwood
  • Publication number: 20060094169
    Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Ted White, Alexander Barr, Bich-Yen Nguyen, Marius Orlowski, Mariam Sadaka, Voon-Yew Thean
  • Publication number: 20060084235
    Abstract: A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.
    Type: Application
    Filed: October 15, 2004
    Publication date: April 20, 2006
    Inventors: Alexander Barr, Olubunmi Adetutu, Bich-Yen Nguyen, Marius Orlowski, Mariam Sadaka, Voon-Yew Thean, Ted White
  • Publication number: 20060084207
    Abstract: P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide P channel transistor performance enhancement, the direction of their channel lengths is selected based on their channel direction. The narrow width P channel transistors are preferably oriented in the <100> direction. The wide channel width P channel transistors are preferably oriented in the <110> direction.
    Type: Application
    Filed: October 20, 2004
    Publication date: April 20, 2006
    Inventors: Ted White, Alexander Barr, Dejan Jovanovic, Bich-Yen Nguyen, Mariam Sadaka, Voon-Yew Thean
  • Publication number: 20060065927
    Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Voon-Yew Thean, Mariam Sadaka, Ted White, Alexander Barr, Venkat Kolagunta, Bich-Yen Nguyen, Victor Vartanian, Da Zhang
  • Publication number: 20060068553
    Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Voon-Yew Thean, Mariam Sadaka, Ted White, Alexander Barr, Venkat Kolagunta, Bich-Yen Nguyen, Victor Vartanian, Da Zhang