Abstract: A battery component includes a header body and a frame secured to the header body. The frame includes an electromagnetic shield portion. The electromagnetic shield portion defines at least one electrical connection port. The electrical connection port is configured to receive an electrically conductive object. The electromagnetic shield portion is configured to dissipate electromagnetic radiation from the electrically conductive object.

Abstract: A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.

Abstract: A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.

Abstract: A powered high-speed cutting tool that also locates objects behind sheet material and subsequently cuts around the object. The tool incorporates at least one sensor having a transceiver emitting a signal to detect at least one from the group of object density, conductivity, distance, and identification. The sensor is housed within a sensor unit that is part of the body of the cutting tool. The sensor unit can be incorporated into the body or removable from the cutting tool. A marking unit is used to mark the cutting area of the sheet material and is generally part of or located near a sensor unit. Indicator members, such as lights, audio, and/or display screen, are used to provide information to the user.

Abstract: A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.

Abstract: A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.

Abstract: A powered high-speed cutting tool that also locates objects behind sheet material and subsequently cuts around the object. The tool incorporates at least one sensor having a transceiver emitting a signal to detect at least one from the group of object density, conductivity, distance, and identification. The sensor is housed within a sensor unit that is part of the body of the cutting tool. The sensor unit can be incorporated into the body or removable from the cutting tool. A marking unit is used to mark the cutting area of the sheet material and is generally part of or located near a sensor unit. Indicator members, such as lights, audio, and/or display screen, are used to provide information to the user.

Abstract: A powered high-speed cutting tool that also locates objects behind sheet material and subsequently cuts around the object. The tool incorporates at least one sensor having a transceiver emitting a signal to detect at least one from the group of object density, conductivity, distance, and identification. The sensor is housed within a sensor unit that is part of the body of the cutting tool. The sensor unit can be incorporated into the body or removable from the cutting tool. A marking unit is used to mark the cutting area of the sheet material and is generally part of or located near a sensor unit. Indicator members, such as lights, audio, and/or display screen, are used to provide information to the user.

Abstract: A powered cutting tool for locating objects behind sheet material and subsequently cutting around the object. The tool incorporates at least one sensor having a transceiver emitting signal to detect at least one from the group of object density, conductivity, depth, and identification. The sensor is housed within a sensor unit that is affixed to the body of the cutting tool. The sensor unit can be integral with, or removable from, the cutting tool. A marking unit is used to mark the cutting area of the sheet material and is generally integral with, or located near, a sensor unit. Indicator members, such as lights, audio, and/or display screen, are used to provide information to the user.

Abstract: This invention is directed to a method for treating an inflammatory condition, treating haematological and other malignancies, causing immunosuppression, or preventing or treating transplant rejection in man or other animals which comprises administering to a patient a compound that has the structure of Formula (I) or Formula (II) as defined below, or a pharmaceutically acceptable derivative thereof or pro-drug therefor, wherein R?NH2, NHR1, NHOR2, NHNHR2, NHCOR2, and R1?C(1-4)alkyl, C(3-6)cycloalkyl, Cn, where n=1-3, R2=methyl, ethyl, R3=alkyl, cycloalkyl, substituted alkyl, substituted cycloalkyl, aryl, heteroaryl, substituted aryl, or substituted hetrecoaryl; wherein R4, R5?C(1-4)alkyl. Novel compounds according to Formula (III), wherein R6 and R7 are any of H, CH3CO, CH3CH2CO, CH3CH2CH2CO provided that R6 and R7 are not both H, or Formula (IV), wherein R8 and R9 are any of H, CH3CO, CH3CH2CO or CH3CH2CH2CO, having use in such methods, are also described.

Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Abstract: An electrical connector assembly includes an organizer plate having a plurality apertures for receiving termination devices. Each termination device includes a shield box, an insulator, and a socket contact. The shield box has at least one outwardly extending ground contact element and a latch member. When the termination device is inserted into an aperture of the organizer plate, the latch member on the shield box engages a surface of the organizer plate to prevent withdrawal of the termination device.

Abstract: The present invention includes a method of electronically designing an article, including accessing an electronic article design system, selecting an article type to design, and iteratively configuring a group of characteristics by selecting one or more options for each characteristic and/or iteratively modeling the article performance based on a selection of one or more performance parameters for each performance model. In the iterative configuration and modeling step, the electronic article design system automatically presents the characteristics and the performance models based on the article type selected, dynamically updates the article for each step of the iterative configuration and/or modeled performance, and automatically resolves conflicts between iteratively configured characteristics, between iteratively modeled performances, and across iteratively configured characteristics and modeled performances.

Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

Abstract: An electrical interconnection system includes a printed circuit board having a receiving cavity therein. At least one circuit trace is located on a side wall of the cavity. An electrical connector is configured for insertion into the receiving cavity. The electrical connector has an electrical contact positioned to contact the at least one circuit trace when inserted into the receiving cavity.

Abstract: A connector assembly includes a frame mounted on a printed circuit substrate having a plurality of contact pads, and a spring member configured for insertion into the frame. The spring member has a flexible circuit supported thereon. The spring member and frame are shaped to exert biasing forces in two non-parallel directions when the spring member is inserted into the frame.

Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

Abstract: One aspect provides a capacitor feedthrough assembly having an electrically conductive member dimensioned to extend at least partially through a feedthrough hole of a case of the capacitor, the conductive member having a passage therethrough.

Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Abstract: A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.