Patents by Inventor Alexander J. Pasadyn

Alexander J. Pasadyn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030097198
    Abstract: A method and an apparatus for performing feed-forward correction during semiconductor wafer manufacturing. A first process on a semiconductor wafer is performed. Integrated metrology data related to the first process of the semiconductor wafer is acquired. An integrated metrology feed-forward process is performed based upon the integrated metrology data, the integrated metrology feed-forward process comprising identifying at least one error on the semiconductor wafer based upon the integrated metrology data related to the first process of the semiconductor wafer and performing an adjustment process to a second process to be performed on the wafer to compensate for the error. The second process on the semiconductor wafer is performed based upon the adjustment process.
    Type: Application
    Filed: November 16, 2001
    Publication date: May 22, 2003
    Inventors: Thomas J. Sonderman, Alexander J. Pasadyn, Christopher A. Bode
  • Publication number: 20030082837
    Abstract: A method and an apparatus for performing cascade control of processing of semiconductor wafers. A first semiconductor wafer for processing is received. A second semiconductor wafer for processing is received. A cascade processing operation upon the first and the second semiconductor wafers is performed, wherein the cascade processing operation comprises acquiring pre-process metrology data related to the second semiconductor wafer during at least a portion of a time period wherein the first semiconductor wafer is being processed.
    Type: Application
    Filed: October 30, 2001
    Publication date: May 1, 2003
    Inventors: Alexander J. Pasadyn, Christopher A. Bode
  • Patent number: 6540591
    Abstract: A method for polishing wafers includes providing a wafer having a process layer formed thereon; providing a polishing tool having a plurality of control zones and being adapted to polish the process layer based on an operating recipe, the operating recipe having a control variable corresponding to each of the control zones; measuring a pre-polish thickness profile of the process layer; comparing the pre-polish thickness profile to a target thickness profile to determine a desired removal profile; determining values for the control variables associated with the control zones based on the desired removal profile; and modifying the operating recipe of the polishing tool based on the values determined for the control variables. A processing line includes a polishing tool, a metrology tool, and a process controller. The polishing tool is adapted to polish a wafer having a process layer formed thereon based on an operating recipe.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: April 1, 2003
    Inventors: Alexander J. Pasadyn, Christopher H. Raeder, Anthony J. Toprac
  • Patent number: 6534328
    Abstract: The present invention is generally directed to a method of modeling and controlling the endpoint of chemical mechanical polishing operations performed on a process layer, and a system for accomplishing same. In one illustrative embodiment, the method comprises providing a first wafer having a process layer formed thereabove, determining a duration of an endpoint polishing process performed on the process layer on the wafer, providing a second wafer having a process layer formed thereabove, and modifying at least one parameter of the endpoint polishing process to be performed on the process layer formed above the second wafer based upon a variance between the determined duration of the endpoint polishing process performed on the process layer on the first wafer and a target value for the duration of the endpoint polishing process.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: March 18, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joyce S. Oey Hewett, Alexander J. Pasadyn
  • Publication number: 20020177245
    Abstract: A method for controlling critical dimensions of a feature formed on a semiconductor wafer includes illuminating the wafer; measuring light reflected off the wafer to generate a profile trace; comparing the profile trace to a target profile trace; and modifying an operating recipe of a processing tool used to form the feature based on a deviation between the profile trace and the target profile trace. A processing line includes a processing tool, a scatterometer, and a process controller. The processing tool is adapted to form a feature on a semiconductor wafer in accordance with an operating recipe. The scatterometer is adapted to receive the wafer. The scatterometer includes a light source adapted to illuminate the wafer and a light detector adapted to measure light from the light source reflected off the wafer to generate a profile trace.
    Type: Application
    Filed: March 29, 2001
    Publication date: November 28, 2002
    Inventors: Thomas J. Sonderman, Christopher A. Bode, Alexander J. Pasadyn, Anthony J. Toprac, Joyce S. Oey Hewett, Anastasia Oshelski Peterson, Michael L. Miller
  • Patent number: 6444481
    Abstract: A method for controlling a plating process includes plating a process layer on a wafer in accordance with a recipe; measuring a thickness of the process layer; and determining at least one plating parameter of the recipe for subsequently formed process layers based on the measured thickness. A processing line includes a plating tool, a metrology tool, and a process controller. The plating tool is adapted to form a process layer on a wafer in accordance with a recipe. The metrology tool is adapted to measure a thickness of the process layer. The process controller is adapted to determine at least one plating parameter of the recipe for subsequently formed process layers based on the measured thickness.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: September 3, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Pasadyn, Thomas J. Sonderman
  • Patent number: 6442496
    Abstract: The present invention provides for a method and an apparatus for performing dynamic sampling of a production line. A first plurality of semiconductor wafers are processed. A minimum sampling rate of semiconductor wafers is calculated. Wafers from the first plurality of the semiconductor wafers are selected and analyzed at the calculated sampling rate. The performance of the processing of the first plurality of semiconductor wafers is quantified, based upon the analyzed wafers. A dynamic sampling process is performed based upon the quantification of the performance of the processing of semiconductor wafers.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: August 27, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Pasadyn, Anthony J. Toprac
  • Publication number: 20020106821
    Abstract: A method of compensating for across-wafer variations in photoresist thickness is provided. The method comprises providing a wafer having a process layer formed there-above, forming a layer of photoresist above the process layer, measuring a thickness of the layer of photoresist at a plurality of locations to result in a plurality of thickness measurements, providing the thickness measurements to a controller that determines, based upon the thickness measurements, an exposure dose of an exposure process to be performed on the layer of photoresist, and performing the exposure process on the layer of photoresist using the determined exposure dose. This exposure dose may be varied on a flash-by-flash basis as the stepper tool “steps” across the surface of wafers. That is, the exposure dose for a group of flashes, or for each flash, may be varied in response to the thickness measurements.
    Type: Application
    Filed: February 2, 2001
    Publication date: August 8, 2002
    Inventors: Christopher A. Bode, Joyce S. Oey Hewett, Alexander J. Pasadyn
  • Publication number: 20020087229
    Abstract: A technique for processing a wafer in a semiconductor manufacturing process are disclosed. The method comprises first collecting a set of processing rate data from a multi-station processing tool, the set including process rate data from at least two stations in the processing tool. The collected processing rate data is then communicated to a controller that autonomously compares the processing rate data to determine whether to adjust a process parameter. The method then adjusts the process parameter for at least one station to match the process endpoint for the at least one station.
    Type: Application
    Filed: January 2, 2001
    Publication date: July 4, 2002
    Inventors: Alexander J. Pasadyn, Joyce S. Oey Hewett