Abstract: A semiconductor structure may include a bottom source drain, a top source drain, a gate stack. The top source drain is above the gate stack and the bottom source drain is below the gate stack. The semiconductor structure may also include a bottom spacer and a top spacer. The gate stack is between the bottom spacer and the top spacer. The bottom spacer and the top spacer each comprise a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the top source drain, and the bottom source drain.

Abstract: A memory structure comprises a ReRAM module embedded in a substrate. An insulative layer is formed on the substrate. A first electrode is located on the insulative layer. The first electrode is proximately connected to a first end of the ReRAM module and comprises a first surface area. A second electrode is located on the insulative layer. The second electrode is proximately connected to a second end of the ReRAM module. The second electrode comprises a second surface area, a plasma-interacting component, and a resistive component. The resistive component is located between the plasma-interacting component and the ReRAM module. A ratio of the first surface area to the second surface area creates a voltage between the first electrode and second electrode when the first surface area and second surfaces area are exposed to an application of plasma. The voltage forms a conductive filament in the ReRAM module.

Abstract: A fork-sheet semiconductor device includes a first-type source/drain region on a substrate and a second-type source/drain region on the substrate and separated from the first-type source/drain region by an insulator pillar. The fork-sheet semiconductor device further includes a first metal portion and a second metal portion. The first metal portion completely covers a first upper surface and a first exposed sidewall the first-type source/drain region and the second metal portion completely covers a second upper surface and a second exposed sidewall the second-type source/drain region. The first and second metal portions are separated from one another by the insulator pillar. A first-type contact portion extends vertically from the first metal portion and an opposing second-type contact portion extends vertically from the second metal portion. A first upper interconnect structure contacts the first-type contact portion and a second upper interconnect structure contacts the second-type contact portion.

Abstract: An electronic circuit includes a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines at a plurality of grid points; and a plurality of resistive random-access memory cells located at the plurality of grid points. Each of the resistive random-access memory cells includes a top metal coupled to one of: a corresponding one of the word lines and a corresponding one of the bit lines; a bottom metal coupled to another one of: the corresponding one of the word lines and the corresponding one of the bit lines; a dielectric sandwiched between the top metal and the bottom metal; and a high-resistance semiconductive spacer electrically connecting the top metal and the bottom metal in parallel with the dielectric.

Abstract: An approach to form a semiconductor structure with a buried power rail. The semiconductor structure includes a buried power rail in a semiconductor substrate where a buried contact contacts to a first portion of a top surface of the buried power rail to a source/drain of a semiconductor device. Additionally, the semiconductor structure includes a first portion of a top surface of the buried contact that is below a top surface of the source/drain of the semiconductor device and a portion of a bottom surface of the buried contact that is in a cavity formed in the source/drain of the semiconductor device.

Abstract: A semiconductor structure including nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material and a crystallized gate dielectric layer surrounding the semiconductor channel layers of a first subset of the nanosheet stacks, a dipole layer on top of the crystallized gate dielectric and surrounding the layers of semiconductor channel material of the first subset of the nanosheet stacks and a gate dielectric modified by a diffused dipole material surrounding the semiconductor channel layers of a second subset of the nanosheet stacks.

Abstract: A pillar bump structure, and a method for forming the same includes forming, on a semiconductor substrate, a blanket liner followed by a seed layer including a noble metal. A first photoresist layer is formed directly above the seed layer followed by the formation of a first plurality of openings within the photoresist layer. A first conductive material is deposited within each of the first plurality of openings to form first pillar bumps. The first photoresist layer is removed from the semiconductor structure followed by removal of portions of the seed layer extending outward from the first pillar bumps, a portion of the seed layer remains underneath the first pillar bumps.

Abstract: An embedded magnetoresistive random-access memory (MRAM) device including a portion of a metal wiring layer above a semiconductor device and a bottom electrode over the portion of the metal wiring layer. The embedded MRAM where the bottom electrode connects to a first portion of a bottom surface of a magnetoresistive random access memory pillar and a sidewall spacer is on the magnetoresistive random access memory pillar. The embedded MRAM device includes a ring of inner metal is on the portion of the metal wiring layer surrounding a portion of the bottom electrode.

Abstract: A semiconductor structure including nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material and a crystallized gate dielectric layer surrounding the semiconductor channel layers of a first subset of the nanosheet stacks, a dipole layer on top of the crystallized gate dielectric and surrounding the layers of semiconductor channel material of the first subset of the nanosheet stacks and a gate dielectric modified by a diffused dipole material surrounding the semiconductor channel layers of a second subset of the nanosheet stacks.

Abstract: A semiconductor structure may include a bottom source drain, a top source drain, a gate stack. The top source drain is above the gate stack and the bottom source drain is below the gate stack. The semiconductor structure may also include a bottom spacer and a top spacer. The gate stack is between the bottom spacer and the top spacer. The bottom spacer and the top spacer each comprise a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the top source drain, and the bottom source drain.

Abstract: A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of first type sacrificial layers and active semiconductor layers. The method includes forming the first type sacrificial layer on sidewalls of the nanosheet stacks, then forming a dielectric pillar between the sidewall portions of the first type sacrificial layers of adjacent nanosheet stacks, and then removing the first type sacrificial layer. The method also includes forming a PWFM layer in spaces formed by the removal of the first type sacrificial layer for a first one of the nanosheet stacks, and includes forming a NWFM layer in spaces formed by the removal of the first type sacrificial layer for an adjacent second one of the nanosheet stacks.

Abstract: A memory device, and a method of making the same, includes a resistive random-access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor consisting of an epitaxially grown material that forms the bottom electrode of the resistive random-access memory element. Additionally, a method of writing to the memory device includes applying a first voltage on a word line of the memory device to form a filament in the resistive random-access memory element. A second voltage including an opposite polarity to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random-access memory element.

Abstract: A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.

Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.

Abstract: A semiconductor device structure comprises at least one semiconductor fin for a vertical transport field effect transistor, a bottosource/drain layer, and an insulating layer underlying the bottom source/drain layer. A method of forming the structure comprises forming a sacrificial layer within a lower portion of a source/drain region for a vertical transport field effect transistor structure. The sacrificial layer being formed adjacent to at least one semiconductor fin and in contact with a substrate. A source/drain layer is formed within an upper portion of the source/drain region above the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the substrate and the source/drain layer. An insulating layer is formed within the cavity.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device on an integrated circuit (IC). The method includes forming a containment structure having a non-sacrificial fin-containment region and a sacrificial fin-containment region, wherein the containment structure is configured to define a source or drain (S/D) cavity. A S/D region is formed in the S/D cavity. The S/D region includes a contained S/D region defined by the containment structure. The S/D region further includes a non-contained S/D region positioned above the containment structure. The IC is exposed to an etchant that is selective to the sacrificial fin-containment region, non-selective to the non-sacrificial fin-containment region, and non-selective to a plurality of spacers on the IC. Exposing the IC to the etchant selectively removes the sacrificial fin-containment region and exposes sidewalls of the contained S/D region.

Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.

Abstract: Embodiments of the invention are directed to a transistor that includes a source or drain (S/D) region having an S/D formation assistance region, wherein the S/D formation assistance region includes a top surface, sidewalls, and a bottom surface. The S/D formation assistance region is at least partially within a portion of a substrate. An S/D isolation region is formed around the sidewalls and the bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.

Abstract: A circuit structure includes a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode is connected to a wordline, and the first source electrode and the second source electrode are connected to a bitline. The first drain electrode is connected to the second gate electrode and the second drain electrode is connected to a bias line. A weight synapse structure is constructed by combining two circuit structures. A plurality of weight synapse structures are incorporated into a crossbar array.

Abstract: A cross-bar ReRAM comprising a substrate, a plurality of first columns extending parallel to each other on the top surface of the substrate, wherein each of the plurality of the first columns includes a resistive random-access memory (ReRAM) stack comprised of a plurality of layers. A plurality of second columns extending parallel to each other and the plurality of second columns extending perpendicular to the plurality of first columns, wherein the plurality of second columns is located on top of the plurality of first columns, such that the plurality of second columns crosses over the plurality of first columns. A dielectric layer filling in the space between the plurality of first columns and the plurality of second columns, wherein the dielectric layer is in direct contact with a sidewall of each of the plurality layers of the ReRAM stack.