Abstract: A semiconductor device, and method of fabricating the device. The device including a plurality of vertical transistors, each vertical transistor having a raised semiconductor island having a first cross-sectional profile, a source-drain region disposed above the raised semiconductor island, the source-drain region having a second cross-sectional profile, and a semiconductor channel disposed above the source-drain region, the semiconductor channel having a third cross-sectional profile. The second cross-sectional profile is asymmetric.

Abstract: A semiconductor structure may include a vertical field effect transistor, the vertical field effect transistor may include a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory below the vertical field effect transistor. The resistive random access memory may include an epitaxial oxide layer, a top electrode, and a bottom electrode. The top electrode, which may function as the bottom source drain of the vertical field effect transistor, may be in direct contact with the epitaxial channel of the vertical field effect transistor. The epitaxial oxide layer may separate the top electrode from the bottom electrode. The top source drain may be arranged between a dielectric material and the epitaxial channel. The dielectric material may be in direct contact with a top surface of the epitaxial channel. The epitaxial oxide layer may be composed of a rare earth oxide.

Abstract: A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.

Abstract: A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of sacrificial layers and active semiconductor layers. The method includes removing portions of the sacrificial layers to form angular indents in each side thereof, then filling the indents with a low-? material layer. The method further includes forming source drain regions between the nanosheet stacks, removing remaining portions of the sacrificial layers, and then forming gate metal layers in spaces formed by the removal of the sacrificial layers.

Abstract: A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

Abstract: A semiconductor structure for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including the SiGe layer and a second material layer formed on the SiGe layer, a first high-? metal gate disposed over the first set of fins, and a second high-? metal gate disposed over the second set of fins. An asymmetric threshold voltage is present along the channel of the VTFET in a region defined at a bottom of the first and second set of fins, and a Ge content of the second material layer is higher than a Ge content of the SiGe layer.

Abstract: A method of forming a semiconductor device includes forming a sacrificial epitaxial layer upon a substrate, forming a stack of semiconductor material layers upon the sacrificial epitaxial layer, forming fin mandrels for vertical transistors, selectively etching the sacrificial epitaxial layer beneath the fin mandrels, forming source-drain regions beneath the fin mandrels, selectively removing portions of the fin mandrels creating the fins, and forming source-drain contacts electrically connected to the source-drain regions.

Abstract: A semiconductor structure may include a buried power rail under a bottom source drain of a vertical transistor and a dielectric bi-layer under the bottom source drain. The dielectric bi-layer may be between the buried power rail and the bottom source drain. The semiconductor structure may include a silicon germanium bi-layer under the bottom source drain, the silicon germanium bi-layer may be adjacent to the buried power rail. The semiconductor structure may include a buried power rail contact. The buried power rail contact may connect the bottom source drain to the buried power rail. The dielectric bi-layer may include a first dielectric layer and a dielectric liner. The first dielectric layer may be in direct contact with the bottom source drain. The dielectric liner may surround the buried power rail. The silicon germanium bi-layer may include a first semiconductor layer and a second semiconductor layer below the first semiconductor layer.

Abstract: A Vertical Reconfigurable Field Effect Transistor (VRFET) has a substrate and a vertical channel. The vertical channel is in contact with a top silicide region that forms a lower Schottky junction with the vertical channel and a top silicide region that forms an upper Schottky junction with the vertical channel. The lower silicide region and the upper silicide region each form a source/drain (S/D) of the device. A lower gate stack surrounds the vertical channel and has a lower overlap that encompasses the lower Schottky junction. An upper gate stack surrounds the vertical channel and has an upper overlap that encompasses the upper Schottky junction. The lower gate stack is electrically insulated from the upper gate stack. The lower gate stack can electrically control the lower Schottky junction (S/D). The upper gate stack can electrically control the upper Schottky junction (S/D).

Abstract: A method of forming a vertical transport fin field effect transistor device is provided. The method includes replacing a portion of a sacrificial exclusion layer between one or more vertical fins and a substrate with a temporary inner spacer. The method further includes removing a portion of a fin layer and the sacrificial exclusion layer between the one or more vertical fins and the substrate, and forming a bottom source/drain on the temporary inner spacer and between the one or more vertical fins and the substrate. The method further includes replacing a portion of the bottom source/drain with a temporary gap filler, and replacing the temporary gap filler and temporary inner spacer with a wrap-around source/drain contact having an L-shaped cross-section.

Abstract: Arrays of PCM devices and techniques for fabrication thereof having an integrated resistor formed during heater patterning for uniform voltage drop amongst the PCM devices are provided. In one aspect, a PCM device includes: at least one PCM cell including a phase change material disposed on a heater; and at least one resistor in series with the at least one PCM cell, wherein the at least one resistor includes a same combination of materials as the heater. A memory array and a method of forming a PCM device are also provided.

Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of the fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.

Abstract: A method is presented for reducing sagging effects in nanosheet devices. The method includes forming at least two nanosheet structures over a substrate, wherein each nanosheet structure includes alternating layers of a first semiconductor material and a second semiconductor material, depositing a dielectric layer over the at least two nanosheet structures, depositing a dummy gate over the dielectric layer, etching the first semiconductor material to create voids filled with inner spacers, removing the dummy gate and the dielectric layer such that a supporting dielectric section remains between the at least two nanosheet structures, and removing the etched first semiconductor material such that a supporting structure is defined including the supporting dielectric section and the second semiconductor material.

Abstract: A pillar bump structure, and a method for forming the same includes forming, on a semiconductor substrate, a blanket liner followed by a seed layer including a noble metal. A first photoresist layer is formed directly above the seed layer followed by the formation of a first plurality of openings within the photoresist layer. A first conductive material is deposited within each of the first plurality of openings to form first pillar bumps. The first photoresist layer is removed from the semiconductor structure followed by removal of portions of the seed layer extending outward from the first pillar bumps, a portion of the seed layer remains underneath the first pillar bumps.

Abstract: After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer.

Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.

Abstract: A semiconductor device including a first nanosheet stack of two memory cells including a lower nanosheet stack on a substrate including alternating layers of a first work function metal and a semiconductor channel material vertically aligned and stacked one on top of another, and an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material vertically aligned and stacked one on top of another, the upper nanosheet stack vertically aligned and stacked on the lower nanosheet stack, where a first memory cell of the two memory cells including the lower nanosheet stack includes a first threshold voltage and a second memory cell of the two memory cells including the upper nanosheet stack includes a second threshold voltage, where the first threshold voltage is different than the second threshold voltage. Forming a semiconductor device including a first nanosheet stack of two memory cells.

Abstract: A cross-coupled inverter made of nanolayers from a nanosheet stack structure has a left field effect transistor (FET) stack and a right FET stack. The left FET stack has a second left FET stacked on a first left FET. The first and second left FETs have opposite types. The right FET stack has a second right FET stacked on a first right FET. The first and second right FETs have opposite types. The first left and first right FET have a first common source drain (S/D). The left FET stack has a left gate stack surrounding the one or more first left FET channel layers and the one or more second left FET channel layers. The right FET stack has a right gate stack surrounding the one or more first right FET channel layers and the one or more second right FET channel layers. In some embodiments the left/right gate stack has a left/right center gate stack layer and one or more left/right gate stack layers. The center gate stack layers are thicker than the gate stack layers and are between the first and second FETs.