Patents by Inventor Alexandre Sarafianos

Alexandre Sarafianos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190172759
    Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 6, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Abderrezak MARZAKI
  • Publication number: 20190147771
    Abstract: In an embodiment, a circuit includes a supply terminal, a reference terminal, a logic circuit coupled between the supply terminal and the reference terminal, and an auxiliary circuit coupled to the logic circuit. The auxiliary circuit includes a plurality of switches configured to be controlled to produce random criterions. Each random criterion causes, on each transition of an output signal of the logic, an attenuation of a current flowing between a supply terminal of the circuit and a reference terminal of the circuit; or an increase of the current flowing between the supply terminal of the circuit and the reference terminal of the circuit; or an additional current flowing through the logic circuit on a current path not passing through the supply terminal; or no change in the current flowing between the supply terminal of the circuit and the reference terminal of the circuit.
    Type: Application
    Filed: November 12, 2018
    Publication date: May 16, 2019
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge
  • Publication number: 20190122090
    Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Publication number: 20190109100
    Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.
    Type: Application
    Filed: October 8, 2018
    Publication date: April 11, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Abderrezak MARZAKI
  • Publication number: 20190081011
    Abstract: An electronic integrated circuit includes a semiconductor substrate having a rear face. A device for detecting a thinning of the semiconductor substrate via its rear face is formed by a p-n junction that is biased into conduction. Thinning of the substrate is detected by monitoring a current flowing through the p-n junction, and comparing that current to a threshold. In the event the compared current indicates no thinning of the semiconductor substrate, the circuitry for biasing and comparing is deactivated.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 14, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Abderrezak MARZAKI
  • Publication number: 20190079133
    Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 14, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Thomas ORDAS
  • Publication number: 20190051643
    Abstract: A circuit for protecting an integrated circuit against fault injection attacks includes an element including a dielectric which is destroyed, resulting in the occurrence of a short-circuit. The element is connected between two terminals that receive a power supply voltage of the integrated circuit.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 14, 2019
    Inventors: Daniele Fronte, Pierre-Yvan Liardet, Alexandre Sarafianos
  • Publication number: 20190051723
    Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.
    Type: Application
    Filed: October 16, 2018
    Publication date: February 14, 2019
    Inventors: Clement Champeix, Nicolas Borrel, Alexandre Sarafianos
  • Patent number: 10198683
    Abstract: An electronic device randomly modifies a current profile of a logic circuit by using an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 5, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Publication number: 20180373899
    Abstract: A circuit module of an integrated circuit is located in a first zone of a semiconductor substrate. A decoy cell includes an antenna above a second zone of the semiconductor substrate. The second zone is different from the first zone. A generation circuit operates to generate a decoy electrical signal on the basis of a first electrical signal that is characteristic of an operation of the circuit module and of at least one pseudo-random parameter. The decoy electrical signal is circulated through the antenna so as to generate a decoy electromagnetic radiation.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 27, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Thomas ORDAS, Alexandre SARAFIANOS
  • Patent number: 10148421
    Abstract: A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: December 4, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Thomas Ordas, Alexandre Sarafianos, Stephane Chesnais, Fabrice Marinet
  • Publication number: 20180341788
    Abstract: A device can be used for detecting faults. A shift register is suitable for shifting, in tempo with a clock, a binary signal alternating between two logic levels, in successive cells of the shift register. A first logic circuit is suitable for comparing values contained in at least one pair of cells of the register.
    Type: Application
    Filed: March 14, 2018
    Publication date: November 29, 2018
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Patent number: 10141396
    Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: November 27, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Clement Champeix, Nicolas Borrel, Alexandre Sarafianos
  • Patent number: 10079215
    Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 18, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Mathieu Lisart, Jimmy Fort
  • Publication number: 20180261560
    Abstract: An electronic chip including a plurality of buried doped bars and a circuit for detecting an anomaly of an electric characteristic of the bars.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 13, 2018
    Inventors: Alexandre SARAFIANOS, Jimmy FORT, Thierry SOUDE
  • Publication number: 20180253633
    Abstract: In some embodiments, an electronic chip includes a doped semiconductor substrate of a first conductivity type, and wells of the second conductivity type on the side of the front face of the chip, in and on which wells circuit elements are formed. One or more slabs of a second conductivity type are buried under the wells and are separated from the wells. The electronic chip also includes, for each buried slab, a biasable section of the second conductivity type, which extends from the front face of the substrate to the buried slab. A first MOS transistor with a channel of the first conductivity type is disposed in the upper portion of each section, where the first transistor is an element of a flip-flop. A circuit is used for detecting a change in the logic level of one of the flip-flops.
    Type: Application
    Filed: November 2, 2017
    Publication date: September 6, 2018
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Patent number: 10063239
    Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 28, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Bruno Nicolas
  • Publication number: 20180189624
    Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
    Type: Application
    Filed: October 31, 2017
    Publication date: July 5, 2018
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Publication number: 20180097058
    Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.
    Type: Application
    Filed: February 28, 2017
    Publication date: April 5, 2018
    Inventors: Clement Champeix, Nicolas Borrel, Alexandre Sarafianos
  • Publication number: 20180094973
    Abstract: A laser detection device can be used to protect an integrated circuit. The device includes a detection cell having a buried channel of a first conductivity type extending in a substrate of the integrated circuit. The substrate is of a second conductivity type. The detection cell also has a first electrical connection coupling a first point in the buried channel to a supply voltage rail, and a second electrical connection coupled to a second point in the buried channel. A detection circuit is coupled to the second point in the buried channel via the second electrical connection and adapted to detect a fall in the voltage at the second point.
    Type: Application
    Filed: February 28, 2017
    Publication date: April 5, 2018
    Inventors: Alexandre Sarafianos, Clement Champeix