Patents by Inventor Alexandre Sarafianos

Alexandre Sarafianos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150194393
    Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.
    Type: Application
    Filed: March 24, 2015
    Publication date: July 9, 2015
    Inventors: Mathieu LISART, Sylvie WUIDART, Alexandre SARAFIANOS
  • Patent number: 9070697
    Abstract: A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: June 30, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Jimmy Fort, Alexandre Sarafianos, Julien Mercier
  • Patent number: 9012911
    Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Sylvie Wuidart, Mathieu Lisart, Alexandre Sarafianos
  • Publication number: 20150048459
    Abstract: A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 19, 2015
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Jimmy Fort, Alexandre Sarafianos, Julien Mercier
  • Patent number: 8946859
    Abstract: An integrated circuit chip including a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type, and a device of protection against attacks including: between the wells, trenches with insulated walls filled with a conductive material, said trenches extending from the upper surface of the wells to the substrate; and a circuit capable of detecting a modification of the stray capacitance formed between said conductive material and a region of the chip.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: February 3, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Alexandre Sarafianos
  • Patent number: 8907452
    Abstract: A device for detecting a laser attack in an integrated circuit chip formed in the upper P-type portion of a semiconductor substrate incorporating an NPN bipolar transistor having an N-type buried layer, including a detector of the variations of the current flowing between the base of said NPN bipolar transistor and the substrate.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Jimmy Fort, Alexandre Sarafianos, Julien Mercier
  • Patent number: 8809858
    Abstract: An integrated circuit including: a semiconductor substrate of a first conductivity type having at least one well of a second conductivity type laterally delimited, on two opposite walls, by regions of the first conductivity type, defined at its surface; at least one region of the second conductivity type which extends in the semiconductor substrate under the well; and a system for detecting a variation of the substrate resistance between each association of two adjacent regions of the first conductivity type.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: August 19, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Thierry Soudé, Alexandre Sarafianos, Francesco La Rosa
  • Patent number: 8796765
    Abstract: An integrated circuit chip includes: a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type; in each well of the first type, a plurality of MOS transistors having a channel of the second conductivity type, and in each well of the second type, a plurality of MOS transistors having a channel of the first type, transistors of neighboring wells being inverted-connected; and a device of protection against attacks, including: a layer of the second type extending under said plurality of wells, from the lower surface of said wells; and regions of lateral insulation between the wells, said regions extending from the upper surface of the wells to said layer.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Alexandre Sarafianos, Olivier Gagliano, Marc Mantelli
  • Publication number: 20140138686
    Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 22, 2014
    Applicant: ST Microelectronics (Rousset) SAS
    Inventors: Sylvie Wuidart, Mathieu Lisart, Alexandre Sarafianos
  • Publication number: 20120320477
    Abstract: An integrated circuit chip including a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type, and a device of protection against attacks including: between the wells, trenches with insulated walls filled with a conductive material, said trenches extending from the upper surface of the wells to the substrate; and a circuit capable of detecting a modification of the stray capacitance formed between said conductive material and a region of the chip.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 20, 2012
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Alexandre Sarafianos
  • Publication number: 20120320480
    Abstract: An integrated circuit chip includes: a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type; in each well of the first type, a plurality of MOS transistors having a channel of the second conductivity type, and in each well of the second type, a plurality of MOS transistors having a channel of the first type, transistors of neighboring wells being inverted-connected; and a device of protection against attacks, including: a layer of the second type extending under said plurality of wells, from the lower surface of said wells; and regions of lateral insulation between the wells, said regions extending from the upper surface of the wells to said layer.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 20, 2012
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mathieu Lisart, Alexandre Sarafianos, Olivier Gagliano, Marc Mantelli