Abstract: A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.

Abstract: A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

Abstract: A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

Abstract: A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

Abstract: A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.

Abstract: A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.

Abstract: A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.

Abstract: A method of monitoring supply voltage includes providing a single reference voltage, providing a single ratioed supply voltage, comparing the reference voltage to the ratioed supply voltage to provide an output signal, wherein the output signal comprises a first logic value in first and second operating conditions, and a second logic value in a third operating condition, wherein the first, second, and third operating conditions are determined by two crossing points of the reference voltage and ratioed supply voltage characteristics. The first and second operating conditions can represent undervoltage and overvoltage conditions, and the third operating condition can represent a normal operating condition. The reference voltage can be provided by a bandgap reference circuit.

Abstract: A method of monitoring supply voltage includes providing a single reference voltage, providing a single ratioed supply voltage, comparing the reference voltage to the ratioed supply voltage to provide an output signal, wherein the output signal comprises a first logic value in first and second operating conditions, and a second logic value in a third operating condition, wherein the first, second, and third operating conditions are determined by two crossing points of the reference voltage and ratioed supply voltage characteristics. The first and second operating conditions can represent undervoltage and overvoltage conditions, and the third operating condition can represent a normal operating condition. The reference voltage can be provided by a bandgap reference circuit.

Abstract: An amplitude-stabilized third-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a plurality of replica cells having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a plurality of control circuits coupled to the differential outputs of the replica cells, and driving the load control inputs of the replica cells and the weighted inputs of a signal combiner driving the load control input of the main cell. The main cell and the replica cells each include a cross-coupled differential cell having a variable load.

Abstract: An amplitude-stabilized second-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a replica cell having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a control circuit coupled to the differential output of the replica cell and driving the load control inputs of the main cell and the replica cell. The main cell and the replica cell are multiplier cells each having a variable load. The control circuit includes a first amplifier for generating a single-ended peak signal and a second amplifier for generating the load control voltage from the difference between the replica cell single-ended peak output signal and a single-ended peak reference signal.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A regulator circuit includes a voltage regulator having a stability control input and an output for providing a regulated output voltage, an amplifier circuit having an input for receiving an error voltage of the voltage regulator, and an output, and a control circuit having an input coupled to the output of the amplifier and an output coupled to the stability control input of the voltage regulator, such that the regulator stability is maximized while the error voltage is minimized. The voltage regulator includes an LDO voltage regulator, the amplifier circuit includes an operational amplifier circuit, and the control circuit includes a load-sensing or load-replicating circuit.

Abstract: An amplitude-stabilized third-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a plurality of replica cells having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a plurality of control circuits coupled to the differential outputs of the replica cells, and driving the load control inputs of the replica cells and the weighted inputs of a signal combiner driving the load control input of the main cell. The main cell and the replica cells each include a cross-coupled differential cell having a variable load.

Abstract: Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an output providing a reference voltage level for its respective Flash comparator. The Flash comparators compare the analog input signal to their respective reference voltage and provide a digital output signal based on the comparison.