Abstract: A preamplifier that is substantially resilient to temperature and input common-mode variations includes a feedback network coupled to regulate a common mode voltage of the preamplifier. The preamplifier can be implemented as a first stage of a multi-stage op amp, which provides an intermediate output to a next stage of the op amp. The feedback and associated temperature stability can be facilitated by downshifting the output voltage of the preamplifier and increasing the output impedance of the preamplifier.

Abstract: The opamp with a slew rate booster includes a first high side transistor 23 coupled to a first differential output node OUT−; a second high side transistor 26 coupled to a second differential output node OUT+; a first booster circuit 72 coupled to the control node of the first high side transistor 23; a second booster circuit 70 coupled to the control node of the second high side transistor 26. The opamp exploits the gate control available on the high side transistors 23 and 26. During the charge-discharge differential transient of the load capacitances 58 and 60, the circuit increases the current given by the high side transistor 23 or 26 that is pulling up its output OUT− or OUT+, and reduces by the same amount the current provided at the other output OUT+ or OUT− that is being pulled down by a low side driver 43 or 40. The gate control is accomplished through a simple, symmetrical capacitor-resistor network that implements a basic differentiator.

Abstract: The opamp with a slew rate booster includes a first high side transistor 23 coupled to a first differential output node OUT−; a second high side transistor 26 coupled to a second differential output node OUT+; a first booster circuit 72 coupled to the control node of the first high side transistor 23; a second booster circuit 70 coupled to the control node of the second high side transistor 26. The opamp exploits the gate control available on the high side transistors 23 and 26. During the charge-discharge differential transient of the load capacitances 58 and 60, the circuit increases the current given by the high side transistor 23 or 26 that is pulling up its output OUT− or OUT+, and reduces by the same amount the current provided at the other output OUT+ or OUT− that is being pulled down by a low side driver 43 or 40. The gate control is accomplished through a simple, symmetrical capacitor-resistor network that implements a basic differentiator.