Sense amplifier for bidirectional sensing of memory cells of a non-volatile memory
A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the resultant voltage level on the sensing node used to determine the result of the sensing operation.
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Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery).
Like-numbered elements refer to common components in the different figures.
To increase the amount of data stored on a non-volatile memory device, data can be stored in a multi-level cell (MLC) format, where an individual memory cell can be programmed to multiple different states, where each memory cell can hold more than one bit of data. In memory cells where different data states correspond to different threshold voltage (Vt) values, this involves splitting up the range, or window, of available Vt values into a number of ranges corresponding to the different data states. To store more states per cell, the Vt range allotted to each state needs to be made smaller, the size of the window increased, or both. The size of the Vt window can be increased by extending the window further into negative Vt values and having multiple states with negative, or non-positive, Vt values. However, for this to be useful, the memory device must be able to distinguish between different non-positive Vt states.
Sensing negative Vt states by most standard sensing techniques and sense amplifier structures has a number of limitations. In a typical sensing arrangement, the control gate of a memory cell is biased by a read voltage and a bit line connected to sense amplifier is discharged through the memory cell to a source line, where the amount of discharge depends on the value of the read voltage relative to the memory cell's Vt. Under this usual arrangement, reading of negative Vt states uses negative read voltages; however, negative voltages are typically not available on a memory die and their introduction involves complications. Alternately, negative Vt states can be read by raising the source voltage for the memory cell, but this approach can usually only extend to a fairly shallow negative Vt range. To allow for sensing more deeply into the negative Vt range, the following introduces sense amplifier structures and techniques in which the source is discharged through a selected memory cell into the bit line and sense amplifier, reversing the usual direction of current flow through the selected memory cell in a sensing operation.
More specifically, a first set of embodiments for a sense amplifier structure and sensing techniques are described where, in a first phase, the source line is discharged through a selected memory to the corresponding bit line and on into the sense amp. The amount of current discharged in this phase will depend on the conductivity of the memory cell, which in turn depends on the word line voltage supplied to the control gate of the selected memory cell relative to its threshold voltage. A discharge transistor has its control gate connected to the memory cell's discharge path during the first phase, so that the conductivity of the discharge transistor will reflect the conductivity of the selected memory cell. The control gate of the discharge transistor is then set to float at this level. In a second phase, a sense node is then discharged through the discharge transistor: as the conductivity of the discharge transistor reflects the conductivity of the selected memory cell, the rate at which the sense node discharges reflects the conductivity of the memory cell. After discharging the sense node for a sensing period, the level on the sense node is latched for the read result.
To improve accuracy of the sensing operation for the first set of embodiments, elements can be included in the sense amp to reduce noise levels. To reduce noise on the control gate of the discharge transistor when transitioning between phases, a decoupling capacitor can be connected to the control gate. The capacitor can also be biased to adjust for operating conditions, such as temperature, and device processing variations. To reduce noise on the source node of the discharge transistor, an auxiliary keeper current can be supplied through the discharge transistor during the transition between phases and on into the sense node discharge phase.
In another set of embodiments for a sense amplifier, the sense amplifier is operable in a first sensing mode, in which current flows from a selected memory through its corresponding bit line and into the sense amplifier, with the charge from the current accumulating on a sensing node and capacitor. The amount of charge accumulated on the sensing node depends on the state of the selected memory cell. In a second sensing mode, charge is discharged from the sensing node and sensing capacitor through the selected memory cell, where the amount of charge remaining on sensing node depends on the state of the selected memory cell. In either sensing mode, the state of the selected memory is then determined based on the amount of charge on the sensing node after the charging (in the first sensing mode) or discharging (in the second sensing mode) of the sensing node. In the second sensing mode, the sensing node discharges to the selected memory cell's bit line through a path of series connected NMOS transistors. For the first sensing mode, a current path from the selected memory cell to the sensing node includes cascaded PMOS transistors, where the cascaded PMOS transistors are connected in parallel with the series connected NMOS transistors used for the second sensing mode.
In some systems, a controller 122 is included in the same package (e.g., a removable storage card) as the one or more memory die 108. However, in other systems, the controller can be separated from the memory die 108. In some embodiments the controller will be on a different die than the memory die 108. In some embodiments, one controller 122 will communicate with multiple memory die 108. In other embodiments, each memory die 108 has its own controller. Commands and data are transferred between a host 140 and controller 122 via a data bus 120, and between controller 122 and the one or more memory die 108 via lines 118. In one embodiment, memory die 108 includes a set of input and/or output (I/O) pins that connect to lines 118.
Control circuitry 110 cooperates with the read/write circuits 128 to perform memory operations (e.g., write, read, and others) on memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control circuit 116. The state machine 112 provides die-level control of memory operations. In one embodiment, state machine 112 is programmable by software. In other embodiments, state machine 112 does not use software and is completely implemented in hardware (e.g., electrical circuits). In other embodiments, state machine 112 can be replaced by a programmable microcontroller. Control circuitry 110 also includes buffers such as registers, ROM fuses and other storage devices for storing default values such as base voltages and other parameters.
The on-chip address decoder 114 provides an address interface between addresses used by host 140 or controller 122 to the hardware address used by the decoders 124 and 132. Power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. Power control module 116 may include charge pumps for creating voltages. The sense blocks include bit line drivers.
State machine 112 and/or controller 122 (or equivalently functioned circuits), in combination with all or a subset of the other circuits depicted in
The (on-chip or off-chip) controller 122 (which in one embodiment is an electrical circuit) may comprise one or more processors 122c, ROM 122a, RAM 122b, a memory interface (MI) 122d and a host interface (HI) 122e, all of which are interconnected. The storage devices (ROM 122a, RAM 122b) store code (software) such as a set of instructions (including firmware), and one or more processors 122c is/are operable to execute the set of instructions to provide the functionality described herein. Alternatively, or additionally, one or more processors 122c can access code from a storage device in the memory structure, such as a reserved area of memory cells connected to one or more word lines. RAM 122b can be to store data for controller 122, including caching program data (discussed below). Memory interface 122d, in communication with ROM 122a, RAM 122b and processor 122c, is an electrical circuit that provides an electrical interface between controller 122 and one or more memory die 108. For example, memory interface 122d can change the format or timing of signals, provide a buffer, isolate from surges, latch I/O, etc. One or more processors 122c can issue commands to control circuitry 110 (or another component of memory die 108) via Memory Interface 122d. Host interface 122e provides an electrical interface with host 140 data bus 120 in order to receive commands, addresses and/or data from host 140 to provide data and/or status to host 140.
In one embodiment, memory structure 126 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material such as described, for example, in U.S. Pat. No. 9,721,662, incorporated herein by reference in its entirety.
In another embodiment, memory structure 126 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates such as described, for example, in U.S. Pat. No. 9,082,502, incorporated herein by reference in its entirety. Other types of memory cells (e.g., NOR-type flash memory) can also be used.
The exact type of memory array architecture or memory cell included in memory structure 126 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 126. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure 126 include ReRAM memories, magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure 126 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.
One example of a ReRAM, or PCMRAM, cross point memory includes reversible resistance-switching elements arranged in cross point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.
Magnetoresistive memory (MRAM) stores data by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created.
Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. In other embodiments, the memory cells of a PCM memory can have their data state set or reset through use of current pulses. Note that the use of “pulse” in this document does not require a square pulse, but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave.
A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.
Each memory erase block includes many memory cells. The design, size, and organization of a memory erase block depends on the architecture and design for the memory structure 126. As used herein, a memory erase block is a contiguous set of memory cells that share word lines and bit lines; for example, erase block i of
In one embodiment, a memory erase block (see block i) contains a set of NAND strings which are accessed via bit lines (e.g., bit lines BL0-BL69,623) and word lines (WL0, WL1, WL2, WL3).
Each memory erase block and/or each memory storage unit is typically divided into a number of pages. In one embodiment, a page is a unit of programming/writing and a unit of reading. Other units of programming can also be used. One or more pages of data are typically stored in one row of memory cells. For example, one or more pages of data may be stored in memory cells connected to a common word line. A page includes user data and overhead data (also called system data). Overhead data typically includes header information and Error Correction Codes (ECC) that have been calculated from the user data of the sector. The controller (or other component) calculates the ECC when data is being written into the array, and also checks it when data is being read from the array. In one embodiment, a page includes data stored in all memory cells connected to a common word line.
In the example discussed above, the unit of erase is a memory erase block and the unit of programming and reading is a page. Other units of operation can also be used. Data can be stored/written/programmed, read or erased a byte at a time, 1K bytes, 512K bytes, etc. No particular unit of operation is required for the claimed solutions described herein. In some examples, the system programs, erases, and reads at the same unit of operation. In other embodiments, the system programs, erases, and reads at different units of operation. In some examples, the system programs/writes and erases, while in other examples the system only needs to program/write, without the need to erase, because the system can program/write zeros and ones (or other data values) and can thus overwrite previously stored information.
As used herein, a memory storage unit is the set of memory cells representing the smallest storage unit of operation for the memory technology to store/write/program data into the memory structure 126. For example, in one embodiment, the memory storage unit is a page sized to hold 4 KB of data. In certain embodiments, a complete memory storage unit is sized to match the number of physical memory cells across a row of the memory structure 126. In one embodiment, an incomplete memory storage unit has fewer physical memory cells than a complete memory storage unit.
The interface between controller 122 and non-volatile memory die 108 may be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, memory system 100 may be a card-based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, memory system 100 may be part of an embedded memory system. For example, the flash memory may be embedded within the host. In other example, memory system 100 can be in the form of a solid-state drive (SSD).
In some embodiments, non-volatile memory system 100 includes a single channel between controller 122 and non-volatile memory die 108, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, 2, 4, 8 or more channels may exist between the controller and the memory die, depending on controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the controller and the memory die, even if a single channel is shown in the drawings.
As depicted in
The components of controller 122 depicted in
Referring again to modules of the controller 122, a buffer manager/bus control 214 manages buffers in random access memory (RAM) 216 and controls the internal bus arbitration of controller 122. A read only memory (ROM) 218 stores system boot code. Although illustrated in
Front end module 208 includes a host interface 220 and a physical layer interface (PHY) 222 that provide the electrical interface with the host or next level storage controller. The choice of the type of host interface 220 can depend on the type of memory being used. Examples of host interfaces 220 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 220 typically facilitates transfer for data, control signals, and timing signals.
Back end module 210 includes an error correction code (ECC) engine 224 that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the non-volatile memory. A command sequencer 226 generates command sequences, such as program and erase command sequences, to be transmitted to non-volatile memory die 108. A RAID (Redundant Array of Independent Dies) module 228 manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the non-volatile memory system 100. In some cases, the RAID module 228 may be a part of the ECC engine 224. Note that the RAID parity may be added as an extra die or dies as implied by the common name, but it may also be added within the existing die, e.g. as an extra plane, or extra block, or extra WLs within a block. A memory interface 230 provides the command sequences to non-volatile memory die 108 and receives status information from non-volatile memory die 108. In one embodiment, memory interface 230 may be a double data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. A flash control layer 232 controls the overall operation of back end module 210.
One embodiment includes a writing/reading manager 236, which can be used to manage (in conjunction with the circuits on the memory die) the writing and reading of memory cells. In some embodiments, writing/reading manager 236 performs the processes depicted in the flowcharts described below.
Additional components of system 100 illustrated in
The Flash Translation Layer (FTL) or Media Management Layer (MML) 238 may be integrated as part of the flash management that may handle flash errors and interfacing with the host. In particular, MML may be a module in flash management and may be responsible for the internals of NAND management. In particular, the MML 238 may include an algorithm in the memory device firmware which translates writes from the host into writes to the memory structure 126 of die 108. The MML 238 may be needed because: 1) the memory may have limited endurance; 2) the memory structure 126 may only be written in multiples of pages; and/or 3) the memory structure 126 may not be written unless it is erased as a block. The MML 238 understands these potential limitations of the memory structure 126 which may not be visible to the host. Accordingly, the MML 238 attempts to translate the writes from host into writes into the memory structure 126. As described below, erratic bits may be identified and recorded using the MML 238. This recording of erratic bits can be used for evaluating the health of blocks and/or word lines (the memory cells on the word lines).
Controller 122 may interface with one or more memory dies 108. In one embodiment, controller 122 and multiple memory dies (together comprising non-volatile storage system 100) implement a solid-state drive (SSD), which can emulate, replace or be used instead of a hard disk drive inside a host, as a NAS device, in a laptop, in a tablet, in a server, etc. Additionally, the SSD need not be made to work as a hard drive.
Some embodiments of a non-volatile storage system will include one memory die 108 connected to one controller 122. However, other embodiments may include multiple memory die 108 in communication with one or more controllers 122. In one example, the multiple memory die can be grouped into a set of memory packages. Each memory package includes one or more memory die in communication with controller 122. In one embodiment, a memory package includes a printed circuit board (or similar structure) with one or more memory die mounted thereon. In some embodiments, a memory package can include molding material to encase the memory dies of the memory package. In some embodiments, controller 122 is physically separate from any of the memory packages.
Referring to
The memory systems discussed above can be erased, programmed/written and read. At the end of a successful programming process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages (Vts) for erased memory cells, as appropriate.
In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state S0 directly to any of the programmed data states S1-S7. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state S0. Then, a programming process is used to program memory cells directly into data states S1, S2, S3, S4, S5, S6, and/or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and/or from data state S0 to data state S3, and so on. The arrows of
In some embodiments, before step 702, controller 122 would receive host data and an instruction to program from the host, and the controller would run the ECC engine 224 to create code words from the host data, as known in the art and described in more detail below. These code words are the data transmitted in step 706. Controller 122 (e.g., writing/reading manager 236) can also scramble the data prior to programming the data in the memory.
Typically, the program voltage applied to the control gates (via a selected word line) during a program operation is applied as a series of program pulses. Between programming pulses are a set of verify pulses to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 770 of
In step 774, the appropriate memory cells are verified using the appropriate set of verify reference voltages to perform one or more verify operations. In one embodiment, the verification process is performed by applying the testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage.
In step 776, it is determined whether all the memory cells have reached their target threshold voltages (pass). If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 778. If, in 776, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 780.
In step 780, the system counts the number of memory cells that have not yet reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells that have, so far, failed the verify process. This counting can be done by the state machine, the controller, or other logic. In one implementation, each of the sense blocks will store the status (pass/fail) of their respective cells. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state.
In step 782, it is determined whether the count from step 780 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed memory cells is less than or equal to the predetermined limit, than the programming process can stop and a status of “PASS” is reported in step 778. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, step 780 will count the number of failed cells for each sector, each target data state or other unit, and those counts will individually or collectively be compared to a threshold in step 782.
In another embodiment, the predetermined limit can be less than the number of bits that can be corrected by ECC during a read process to allow for future errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), than the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria.
If number of failed memory cells is not less than the predetermined limit, than the programming process continues at step 784 and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 12, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step 788. This is one example of a program fault. If the program counter PC is less than the program limit value PL, then the process continues at step 786 during which time the Program Counter PC is incremented by 1 and the program voltage Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size (e.g., a step size of 0.1-0.5 volts). After step 786, the process loops back to step 772 and another program pulse is applied to the selected word line so that another iteration (steps 772-786) of the programming process of
In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, of
There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used.
In some embodiments, controller 122 receives a request from the host (or a client, user, etc.) to program host data (data received from the host) into the memory system. In some embodiments, controller 122 arranges the host data to be programmed into units of data. For example, controller 122 can arrange the host data into pages, partial pages (a subset of a page), word line units, blocks, jumbo blocks, or other units.
Step 772 of
The storage density of a memory circuit such as in
In the example of
Another approach to sensing negative Vt states, but without negative voltages, is illustrated in
To the right in
The voltage levels and timing for the switches in
Once the switches BLC2 1111 and BLC 1113 are turned off and the gate of the discharge transistor DT 1115 is floating at the level set during the bit line discharge phase, the conductivity of the transistor DT 1115 is based on the conductivity of the selected memory cell. In the sense node discharging phase, the switch XXL 1121 is turned on so that the previously charged sense node SEN and the sense node capacitor Csen 1123 can discharge through discharge transistor DT 1115 along the SEN path. After a discharge time, the value at the SEN node can then be captured by latch 1125. As the discharge rate along the SEN path depends on the gate voltage on the discharge transistor DT 1115, which in turn depends on the state of the selected memory cell, the latched value corresponds to the data state. For a memory cell biased as illustrated in
A number of variations in
To more accurately sense data values, noise during the sensing process should be minimized to the extent practical, particularly when larger number of states are to be stored with the available Vt window. To this end, several techniques can be applied to the sense amp embodiments illustrated in
To reduce noise on the current path through discharge transistor DT 1115, a clamp device and an auxiliary current source, or “keeper current,” can be introduced into the sense amp circuit to clamp the drain voltage of the discharge transistor DT 1115 during sensing. This can help block the possible noise through discharge transistor DT 1115 and provide a current flow through discharge transistor DT 1115 to the node SRCGND. The node SRCGND will typically be a node on a commonly regulated SRCGND line to which the sense amp and other sense amps are connected, so that during a sensing operation all of the connected sense amps may be discharging current into the SRCGND line. The introduction of the auxiliary keeper current helps to remove the critical noise at SRCGND node during sensing.
To reduce noise at the control gate of the discharge transistor DT 1115, a de-coupling capacitor can be introduced to compensate and correct the possible coupling when the switches BLC2 1111 and BLC 1113 switch off to prepare for discharge of sense node. This solution will help to correct the possibly unwanted coupling to the gate of the discharge transistor DT 1115 and provides a more accurate sensing result. The de-coupling capacitor can track operating conditions, such as the temperature, and device corners in order to obtain more accurate sensing results. This can be useful to provide accurate sensing results with temperature dependence and device corners, since the level of how negative a Vt can be sensed may depend on the temperature and device corners.
More explicitly,
After the bit line select switch BLS 1206, the bit line BL 1205 is connected to the internal bit line BLI through switch BLC2 1211, and then through switch BLC 1213 to the central comment sensing node SCOM. The node SCOM is connected through the discharge transistor DT 1215 to allow the node SCOM to discharge to SRCGND. Similar to
To the right on
The embodiment of
As described above with respect to
To reduce noise on the BLI node, and the gate of discharge transistor DT 1215, when the switches BLC2 1211 and BLC 1213 are turned off during the transition, the de-coupling capacitor Cdecop 1212 is introduced. This capacitor helps to compensate and correct for the possibly of unwanted coupling to the gate of the discharge transistor DT 1215 and provide a more accurate sensing result. The lower plate of Cdecop 1212 is connected to the BLI node, with the upper plate connected to a level BLI BST that can allow the de-coupling capacitor Cdecop 1212 to track the operating conditions, such as temperature, and device corners in order to obtain a more accurate sensing result. In some embodiments, Cdecop 1212 can be implemented as a transistor with both its source and drain connected to the BLI node and its control gate connected to the level BLI BST.
Another source of noise during the transition between phases and the subsequent discharging of the SEN node can come from noise in the SRCGND level, where the SRCGND line will typically be shared by a large number of sense amps that will concurrently be dumping current into the SRCGND line. A supplemental current source through the switch NLO 1218 is connected to a sense amp voltage LVSA to provide a keeper current through the discharge transistor 1215. A clamp device DCL 1219 clamps the drain voltage (at node DCOM) of discharge transistor DT 1215 during the sensing. These devices help block the possible noise through discharge transistor DT 1215 and keep a constant current through to the commonly regulated node SRCGND. This can help remove the detrimental noise at SRCGND node during sensing.
The control signals for some of the devices in
Starting at t0 for
Between t1 and t2, the initial levels for the sense amp are set. The SRCGND line is raised to an initial high value and NLO2 1207 is turned on, as is BLC2 1211. This sets the values on BL 1205 and the node at BLI high. Once the bit line and internal bit line are set, between t2 and t3, NLO2 is turned off and SRCGND is lowered to the level used during the following discharge phases.
The first discharge phase along the first discharge path labelled BL path in
At t6, BLC2 1211 and BLC 1213 are turned off, isolating the BLI node, so that from t7 on, BLI is floating (represented by the broken lines) at a level based the memory cell's conductivity. This cuts off the discharge path from the source line SRC 1203 and causes the bit line 1205 to go high, where it will stay for the rest of the process, and SCOM to discharge through the discharge transistor DT 1215 and bounce about. This also results in coupling noise on BLI and the gate of DT 1215, as illustrated in
The fluctuations on the SCOM node and the BLI node also introduce noise on SRCGND, which can be very sensitive to noise, as shown by the jagged outline of SRCGNE between t6 and t7. To help remove this noise, the supplemental current from NLO 1218 and the clamp DCL 1219 to keep the level at DCOM help to stabilize the SRCGND node and the SCOM node. As shown on the bottom trace, NLO 1218 is turned on to provide the supplemental keeper current at t7.
At t6, the SEN node has been pre-charged and the control gate of DT 1215 and SRCGND have be stabilized. XXL 1221 is then turned on to discharge the SEN node. The transition in XXL 1221 can again introduce noise for SRCGND, which the keeper current from NLO 1218 will also help stabilize. When XXL 1221 turns on at t8, SCOM and SEN begin to discharge at a rate determine by the gate voltage on DT 1215, which was in turn set by the conductivity of the memory cell. As shown, between t8 and t9 the HC state discharges most rapidly and the NC state shows almost no discharge, while the MC state falls in the middle. At t9-t10, the level on SEN is latched, after which the sensing operation is complete.
In step 1405, the switch BLC 1213 is turned on and the source SRC 1203 begins the first discharging phase through the selected memory cell 1201 along the first discharge path (BL path), eventually stabilizing at a level depending on the conductivity of the selected memory cell 1201. The level on BLI during this process is also the level on the control gate of the discharge transistor DT 1215, corresponding to step 1407. Steps 1405 and 1407 are during the period t3-t6 of
The SEN node is pre-charged at step 1409. In the embodiment of
Steps 1411 and 1413 are part of the transition between the two phases, corresponding to the period t6-t8 in the embodiment of
The second discharge phase for the second discharge path, the SEN path, corresponding to the period t8-t9, begins at step 1415. The switch XXL 1221 is turned on and the SEN node discharges through DT 1215, whose control gate was set based on the conductivity of the selected memory cell 1201 at step 1407. For the embodiment of
The discussion now considers an additional set of embodiments for a sense amplifier circuit, such as can be used for determining the data states of non-volatile memory cells. These additional embodiments can include many of the components of the embodiments described above, but can also include additional elements. More specifically, these additional embodiments include a first path and a second path between a selected bit line and the SEN node to which the sensing capacitor, CSEN, is attached. The first path is used for performing sensing operations in a first mode, in which current conducted through a selected memory cell flows into the sense amplifier and is conducted along the first path to the SEN node to charge up the sensing capacitor. The second path is used for conventional sensing operation in which charge on the sensing capacitor is conducted along the second path and discharged through a selected memory cell. In both modes, the voltage level on the SEN node can then be used to determine the data state of the selected memory cell.
The first current path, used when the sensing is based on currently flowing into the sense amplifier, uses PMOS transistors for conducting current from the bit line to the sensing node. The second current path, used when the sensing is based on currently flowing out of sense amplifier, uses NMOS transistors for conducting current from the sensing node to the bit line. The PMOS devices of the first path are in parallel with the NMOS devices of the second current path. Both sensing directions can be achieved by use of a different set of control signals to bias the sense amplifier, so that the sense amplifier is capable to handle the current of a selected memory cell in both directions.
More specifically, starting on the left hand side,
BLI is connected to the common node SCOM of the sense amplifier through a bit line clamp switch BLC 1513, again implemented as an NMOS device, and the SCOM node is in turn connected to the sense node SEN though the NMOS device of switch XXL 1521. The sensing capacitor Csen 1523 is connected to the SEN on its top (as represented here) plate and to the control signal CLKSA on its bottom plate. The sensing node SEN is connected to the data latch 1525. Depending on the embodiment, each sense amplifier can be connected to a number of different data latches, such as can be used for different bits stored on a memory cell when used with a multi-level cells (MLC) memory. The common node SCOM is also connectable to the level VHSA though the NMOS device of switch XXL 1541 and to the level SRCGND thought the NMOS device of switch NLO 1518.
Other elements in
Between the sensing node SEN and the latch 1525 is an NMOS device switch BLQ 1571, where the internal sensing bus line between BLQ 1571 and latch 1525 is labelled SBUS. The internal sensing bus line SBUS is also connectable to the level VHLB by NMOS device switch LPC 1573 that can be used to pre-charge the line SBUS. SBUS is also connected to the level VLOP through the series connected NMOS devices of switch STB 1567 and 1565, whose gate is connected to the SEN node. The NMOS devices 1565 and STB 1567 can be used to discharge the SBUS mode during a sensing operation.
The elements of
More specifically, in parallel with the NMOS device BLC 1513 between BLI and SCOM is the PMOS device PBLC 1514. Between SCOM and SEN, a PMOS PXXL 1522 is connected in parallel with the NMOS XXL 1521. A PMOS switch PBLX 1542 is also connected in parallel with NMOS BLX 1541 for use in the first sensing mode. Before describing the operation of the circuit of
In a traditional sensing operation (second sensing mode) of a sense amplifier, a selected memory cell 1501 is biased by setting the word line WL 1502 to a read voltage. The read voltage is applied to the word line 1502 of the selected memory cell and, in the case of a NAND string, would also include biasing the non-selected memory cells and select gates to be conducting. The degree to which the selected memory cell 1501 conducts depends on the level of the read voltage applied to the word line of the selected memory cell relative the threshold voltage of the memory cell, which in turn depends on the data state programmed to the memory cell.
To perform a sensing operation, either a data read or a program verify in the second mode, the SEN node and sensing capacitor Csen 1523 are pre-charged. The SEN node is pre-charged and then discharged along the path from SEN to BL 1505 through XXL 1521 and BLC 1513 at a rate dependent on the conductivity of the memory cell 1501, which in turn depends on the read voltage applied to WL 1502 relative to the threshold voltage of the memory cell 1501. The voltage level on SEN and Csen 1523 determines the level on the gate of 1565, which determines the conductivity of 1565. The voltage on SBUS can also be pre-charged through LPC 1573. After allowing the SEN node to discharge for some interval of time, the strobe transistor STB 1567 is turned on for a sensing, or strobe, interval to allow SBUS to discharge at a rate dependent of the SENS voltage level. Depending on the level on the internal bus line SBUS at the end of the strobing interval, either a 0 or a 1 sensing result is latched into the latch 1525 based on whether the SBUS voltage level is above or below a reference level.
Once the sense amplifier is biased to its pre-charge levels at steps 1601 and 1603 and the selected memory cell 1501 (or NAND string) is biased at step 1605, the SEN node is discharged along the second current path through XXL 1521 and BLC 1513 to BL 1505 at step 1607. The rate at which the SEN discharges will depend on the conductivity of memory cell 1501, which, in the case of a NAND memory cell, in turn depends on the level of the read voltage applied to word line 1502 relative to the threshold voltage of the memory cell 1501. For example, if the read voltage is less than the memory cell's threshold voltage memory cell 1501 will not conduct and SEN will not discharge. As the gate of 1565 is connected to the SEN node, the voltage on SEN will determine the conductivity of 1565. After allowing an interval for SEN to discharge, at step 1609 a strobe signal of the control signal to STB 1567 is asserted for a strobe interval allowing SBUS to discharge an amount determined by the voltage level on SEN. At the end of the strobe interval, the level on SBUS relative to a reference level is latched into the latch 1525 as either a 0 or 1 to determine the result of the sensing operation.
Once the SEN node and SBUS are pre-charged, the SEN node is discharged through the selected memory cell 1501. The selected memory cell 1501 is biased by setting a read voltage on the word line 1502 and setting the source line CELSRC 1503 to low voltage level. In the case of a NAND string, the non-selected memory cells and selected gates are biased to be conductive. The degree to which the selected memory cell 15011 will conduct will depend on the threshold voltage of the selected memory cell 1501 and the level of the read voltage along word line WL 1502 relative to this threshold value. The series connected, cascaded NMOS switches XXL 1521 and BLC 1513 are on, along with the bit line select switch BLS 1506, with the parallel connected PMOS devices PXXL 1522 and PBLC 1514 of first current path turned off, and the other switches out SCOM (NLO 1518, BLX 1541, PBLX 1542) turned off. This provides the second current path through the source followers of XXL 1521 and BLC 1513 for the SEN node, and the sensing capacitor Csen 1523 to discharge at step 1607 through the selected memory cell 1501 to CELSRC 1503. This is as illustrated by the arrow, where the amount of discharge (or lack of discharge) will depend on the level of the read voltage on WL 1502 relative to the threshold voltage of the selected memory cell 1501.
After a sensing interval for the discharge time, a strobe pulse is applied at STB 1567, corresponding to step 1609. The voltage level on NMOS 1565 is determined by the voltage level on SEN, so that the degree to which SBUS will (or will not) discharge (as represented the arrow to VLOP) will reflect the relationship of the read voltage to the selected memory cells data state as reflected in its threshold voltage. The latching of the level on SBUS at step 1611 can then be performed.
As shown on the right hand side of
With respect to the SEN node, in the stabilization phase (phase 2) the SEN node is discharged to ˜1V, with the local threshold voltage variation of NMOS 1565 compensated for in the result of the discharge. As in
In phase 3, the SBUS line is also pre-charged. With BLQ 1571 and STB 1567 off, LPC 1573 is turned on. This allows for SBUS to be pre-charged form VHLB. Once SBUS is pre-charged, LPC 1573 can be turned off.
Referring back to
When INV_S=low, this indicates that the selected memory cell has passed a preceding program verify and that a subsequent verify operation need not be performed. The memory cell can be locked out from further verify, in which case the bit line BL 1505 need not be discharged for a subsequent verify, saving on power. If INV_S is low, the NMOS 1561 will be off, cutting off the path from bit line BL 1505 through SCOM, PBLX 1542 and the switch of NMOS 1561 to SRCGND. In some modes of operation, such as “no lock-out”, it can be useful to still be able the discharge BL 1505 to SRCGND. To able be able to discharge BL 1505 independently of the INV_S level and without using the PBLX 1542 path, an additional PMOS path between SCOM and SRCGND can be added in parallel with NLO 1518.
The control signals for biasing the elements of the sense amplifier circuit of
The target bit line voltage VBL_TARGET for BL 1505 is received at the node 2301. The value of VBL_TARGET will vary depending on the embodiment, but a typical value can be around 2V, such as some tenths of a volt less to perhaps a volt higher. Relative to VBL_TARGET, the target level of CELSRC for
The target voltage levels of PBLC, PBLX, and PXXL are all lower than VBL_TARGET and are supplied from nodes between 2301 and the low voltage level on the sense amplifier of VSSSA. (As noted above, switches and their control signals are similarly named, so that PBLC, for example, is used for both the PMOS transistor PBLC 1514 and the control signal applied to its control gate.) A diode connected PMOS 2311 connected the VBL_TARGET node 2301 and, though current source 2323, VSSSA provides a first drop down in the voltage of VBL_TARGET. The target voltage for PBLC is provided at node 2313 below the diode connected PMOS 2311. A resistor R1 2315 provides an additional voltage drop for providing the target voltage for PBLX at node 2317, with a second additional voltage drop provided by resistor R2 2319 for the target voltage of PXXL at node 2321.
The input to the circuit of
Steps 2501 and 2503 are part of the pre-charge phase, or phase 1, as illustrated in
Steps 2505 and 2507 are part of the settling or stabilization phase, or phase 2, as illustrated in
Once the sense amplifier has been pre-charged and settled in phases 1 and 2, in phase 3 the selected memory cell 1501 and elements of the sense amplifier are biased to determine the data state stored on the selected memory cell 1501 as illustrated in
The sense amplifier is also biased to accumulate charge on the SEN node and top plate of sensing capacitor Csen 1523 at step 2513, where the amount of charge stored on the SEN node and sensing capacitor Csen 1523 will depend on the data state of the selected memory cell 1501, such as its threshold voltage relative to the sensing voltage applied to the word line WL 1502. In addition to stepping down CLKSA in step 2509 to allow charge to accumulate on the SEN node, PBLC 1514 and PXXL 1522 are turned on, where the voltage levels for the control signals of these devices can be the target values provided from the biasing circuit of
Along with accumulating charge on the SEN node, the SBUS line is also pre-charged in phase 3 at step 2517. By turning LPC 1573 on, and BLQ 1571 and STB 1567 off, SBUS can be pre-charged from VHLB.
Steps 2519, 2521, and 2523 are part of the strobe phase, or phase 4, as illustrated in
According to a first set of aspects, a non-volatile memory circuit includes a plurality of memory cells, a bit line connected to one or more of the memory cells, a sense amplifier connectable to the bit line, and one or more control circuits connected to the memory cells and the sense amplifier. The sense amplifier includes a sensing capacitor and a data latch. The one or more control circuits are configured, in a first sensing mode, to: bias a selected one of the memory cells to conduct current into the sense amplifier at a level dependent on a data state stored in the selected memory cell; bias the sense amplifier accumulate charge on the sensing capacitor to an amount dependent on the level of current conducted into the sense amplifier; and latch a first sensing result into the data latch based on the amount of change accumulated on the sensing capacitor.
Other aspects include a method that includes: biasing a selected memory cell to conduct current into a sense amplifier at a level dependent on a data state stored in the selected memory cell; biasing the sense amplifier accumulate charge on a sensing capacitor of the sense amplifier to an amount dependent on the level of current conducted into the sense amplifier; and latching a sensing result into a data latch based on the amount of charge accumulated on the sensing capacitor.
Yet more aspects include a system that includes a sense amplifier having: a first node connectable to a selected memory cell; a sensing capacitor; a sense node connected to the sensing capacitor; a first path between the first node and the sense node; a second path between the first node and sense node; and one or more biasing circuits. The one or more biasing circuits are configured to: sense the selected memory cell in a first sensing mode by charging the sensing capacitor from current conducted along the first path from the selected memory cell; and sense the selected memory cell in a second sensing mode by discharging the sensing capacitor by current conducted along the second path and through the selected memory cell.
For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.
For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.
For purposes of this document, the term “based on” may be read as “based at least in part on.”
For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.
For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.
The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.
Claims
1. A non-volatile memory circuit, comprising:
- a plurality of memory cells;
- a bit line connected to one or more of the memory cells;
- a sense amplifier connectable to the bit line, comprising: a sensing capacitor; and a data latch; and
- one or more control circuits connected to the memory cells and the sense amplifier and configured, in a first sensing mode, to: bias a selected one of the memory cells to conduct current into the sense amplifier at a level dependent on a data state stored in the selected memory cell; bias the sense amplifier to accumulate charge on the sensing capacitor to an amount dependent on the level of current conducted into the sense amplifier; and latch a first sensing result into the data latch based on the amount of change accumulated on the sensing capacitor.
2. The non-volatile memory circuit of claim 1, the one or more control circuits further configured, in a second sensing mode, to:
- pre-charge the sensing capacitor;
- bias the selected memory cell and the sense amplifier to discharge the sensing capacitor to an amount of charge dependent on the data state stored in the selected memory cell; and
- latch a second sensing result into the data latch based on the amount of change on the sensing capacitor.
3. The non-volatile memory circuit of claim 2, wherein the sense amplifier further comprises:
- a first current path between bit line of the selected memory cell; and
- a second current path, in parallel with the first current path, between the bit line of the selected memory cell,
- wherein the one or more control circuits are further configured to, in the first sensing mode, bias the sense amplifier to accumulate charge on the sensing capacitor through the first current path and, in the second sensing mode, discharge the sensing capacitor through the second current path.
4. The non-volatile memory circuit of claim 3, wherein:
- the first current path includes a plurality of PMOS transistors connected in series between the bit line of the sensing capacitor; and
- the second current path includes a plurality of NMOS transistors connected in series between the bit line of the sensing capacitor.
5. The non-volatile memory circuit of claim 1, wherein:
- the data state stored in the selected memory cell is a negative threshold data state.
6. The non-volatile memory circuit of claim 1, wherein:
- the one or more memory cells, including the selected memory cell, are part of a NAND string; and
- the one or more control circuits are configured to: concurrently with biasing the selected memory cell to conduct current into the sense amplifier at a level dependent on a data state stored in the selected memory cell, bias non-selected memory cells of the NAND string and select gates of the NAND string to a conducting state.
7. A method, comprising:
- biasing a selected memory cell to conduct current into a sense amplifier at a level dependent on a data state stored in the selected memory cell;
- biasing the sense amplifier to accumulate charge on a sensing capacitor of the sense amplifier to an amount dependent on the level of current conducted into the sense amplifier; and
- latching a sensing result into a data latch based on the amount of charge accumulated on the sensing capacitor.
8. The method of claim 7, wherein biasing the sense amplifier accumulate charge on a sensing capacitor of the sense amplifier includes:
- biasing a pair of PMOS transistors connected in series between a bit line to which the selected memory cell is connected and the sensing capacitor to be in an on state.
9. The method of claim 7, wherein latching a sensing result into a data latch based on the amount of charge accumulated on the sensing capacitor includes:
- pre-charging an internal bus line connected to a data latch;
- discharging for a sensing interval the internal bus line through a sensing transistor having a control gate connected to the sensing capacitor; and
- subsequently latching the sensing result in the data latch based a voltage level on the internal bus line.
10. The method of claim 9, wherein biasing the sense amplifier accumulate charge on a sensing capacitor of the sense amplifier includes:
- prior to accumulating charge on the sensing capacitor, pre-charging the sensing capacitor; and
- discharging the sensing capacitor to a level to offset a threshold voltage of the sensing transistor.
11. The method of claim 7, wherein biasing the sense amplifier to accumulate charge on a sensing capacitor of the sense amplifier includes:
- prior to accumulating charge on the sensing capacitor, pre-charging a bit line to which the selected memory cell is connected.
12. The method of claim 11, wherein biasing the sense amplifier accumulate charge on a sensing capacitor of the sense amplifier includes:
- prior to accumulating charge on the sensing capacitor and subsequent to pre-charging the bit line to which the selected memory cell is connected, discharging the bit line to which the selected memory cell is connected through a pair of series connected PMOS devices.
13. A sense amplifier comprising:
- a first node connectable to a selected memory cell;
- a sensing capacitor;
- a sense node connected to the sensing capacitor;
- a first path between the first node and the sense node;
- a second path between the first node and sense node; and
- one or more biasing circuits configured to: sense the selected memory cell in a first sensing mode by charging the sensing capacitor from current conducted along the first path from the selected memory cell; and sense the selected memory cell in a second sensing mode by discharging the sensing capacitor by current conducted along the second path and through the selected memory cell.
14. The sense amplifier of claim 13, wherein:
- the first path includes a first PMOS transistor connected in series with a second PMOS transistor between the first node and the sense node; and
- the second path includes a first NMOS transistor connected in series with a second NMOS transistor between the first node and the sense node, wherein the first PMOS transistor is connected in parallel with the first NMOS transistor and the second PMOS transistor is connected in parallel with the second NMOS.
15. The sense amplifier of claim 14, further comprising:
- a third PMOS transistor,
- wherein the one or more biasing circuits are further configured to: connect the third PMOS transistor in series with the first PMOS transistor in the first sensing mode to discharge first node to a low voltage level.
16. The sense amplifier of claim 15, wherein the one or more biasing circuits are further configured to:
- prior to discharging first node to a low voltage level, pre-charging the first node.
17. The sense amplifier of claim 13, further comprising:
- a bit line select switch whereby the first node is selectively connectable to a plurality of bit lines including a bit line to which the selected memory cell is connected.
18. The sense amplifier of claim 13, further comprising:
- a data latch;
- an internal sensing bus line connected to the data latch; and
- a discharge transistor having a control gate connected to the sense node,
- wherein the one or more biasing circuits are further configured to: subsequent to charging the sensing capacitor in the first sensing mode, discharging the internal sensing bus line through the discharge transistor for a sensing interval; and subsequent to discharging the internal sensing bus line for the sensing interval, latch a sensing result based on a voltage level on the internal sensing bus line into the data latch.
19. The sense amplifier of claim 18, wherein the one or more biasing circuits are further configured to:
- prior to discharging the internal sensing bus line for the sensing interval, pre-charging the internal sensing bus line.
20. The sense amplifier of claim 18, wherein the one or more biasing circuits are further configured to:
- prior to charging the sensing capacitor in the first sensing mode, pre-charge the sensing capacitor and subsequently discharge the sensing capacitor to level to compensate for a threshold voltage of the discharge transistor.
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Type: Grant
Filed: Dec 23, 2019
Date of Patent: Jun 1, 2021
Assignee: SanDisk Technologies LLC (Addison, TX)
Inventors: Yingchang Chen (Cupertino, CA), Seungpil Lee (San Ramon, CA), Ali Al-Shamma (San Jose, CA)
Primary Examiner: Thong Q Le
Application Number: 16/724,896
International Classification: G11C 16/26 (20060101); G11C 16/04 (20060101); G11C 11/56 (20060101);